ARM ARM DUI 0224I manual UARTs block diagram

Hardware Description

Chip		PL011	PrimeCell
ARM926EJ-S Dev.
		PL011	PrimeCell
		PL011	PrimeCell
	AHBM2
FPGA		PL011	PrimeCell

	nDRVINEN1		Versatile Logic Tile
UART0 IrDA signals	nDRVINEN0
UART0x output signals	RS232	SER0x	J10A
UART0x input signals		SER0x
UART1x output signals	RS232	SER1x	J10B
UART1x input signals		SER1x
UART2x output signals	RS232	SER2x	J11A
UART2x input signals		SER2x
UART3x output signals	RS232	SER3x	J11B
UART3x input signals		SER3x

Figure 3-38 UARTs block diagram

The signals from the ARM926EJ-S PXP Development Chip are converted from logic level to RS232 level by MAX3243E buffers as shown in Figure 3-39 and Figure 3-40 on page 3-90.

Figure 3-39 UART0 interface

ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 3-89