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ARM ARM DUI 0224I manual Global Properties, False, True, Jtagclocktype

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Configuring the USB Debug Connection

G.4.1 Global Properties

The Global Properties area of the Debug tab contains settings that control the behavior of the USB debug port when it resets the target hardware. (See Table G-1.)

Table G-1 Reset behavior register names and values

Setting	Register name	Enumerator	Value

Reset Type	RESETOPERATION	nSRST	0x0

		nTRST	0x1

		nSRST + nTRST	0x2

		Fake	0x3

Reset On Disconnect (Default)	RESETONDISCONNECT	FALSE	0x0

		TRUE	0x1

Default Post Reset State	POSTRESETSTATE	Running	0x0

		Stopped	0x1

nSRST Hold Time (ms)	RESETHOLDTIME	-	-

nSRST Post Reset Delay (ms)	POSTRESETDELAY	-	-

nTRST Hold Time (ms)	NTRSTHOLDTIME	-	-

nTRST Post Reset Delay (ms)	NTRSTPOSTRESETTIME	-	-

TAP Reset via State Transitions	DOSOFTTAPRESET	FALSE	0x0

		TRUE	0x1

Target nSRST + nTRST linked	LINKED_SRST_TRST	FALSE	0x0

		TRUE	0x1

JTAG Clock Type	JTAGCLOCKTYPE	Fixed	0x0

		Adaptive	0x1

ARM DUI 0224I

Copyright © 2003-2010 ARM Limited. All rights reserved.

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ARM ARM DUI 0224I manual Global Properties, False, True, Jtagclocktype

Contents

RealView Platform Baseboard for ARM926EJ-S Copyright 2003-2010 ARM Limited. All rights reserved RealView Platform Baseboard for ARM926EJ-SUser Guide Product Status Conformance Notices RealView Platform Baseboard for ARM926EJ-S User Guide Chapter Programmer’s Reference Appendix B Specifications Appendix G Configuring the USB Debug Connection List of Tables Sysmisc VFP9 implementation 100 Xii List of Figures Syssw Sysled Sysbootcs Sysmisc Figure D-4 Jtag signal flow on the PCI backplane Feedback on Preface Intended audience Using this manualAbout this manual Product revision status Typographical Conventions Timing diagrams Numbering Signals ARM publications Further reading Xxiii TFT-LCD Module LQ084V1DG21 Sharp Corporation, Osaka, Japan Other publications Feedback on this manual FeedbackFeedback on this product Xxvi Introduction On page 1-3 shows the layout of the PB926EJ-S About the PB926EJ-S PB926EJ-S layout PB926EJ-S architecture Field Programmable Gate-Array Fpga that implements Time of year clock with backup battery Shows the architecture of the PB926EJ-S System architecture RealView Logic Tile expansion 2 ARM926EJ-S PXP Development Chip3 PB926EJ-S Fpga Displays Debug and test interfaces MemoryClock generators Preventing damage PrecautionsEnsuring safety ARM DUI Getting Started Setting up the RealView Platform Boot memory configuration Setting the configuration switches S1-2 S1-1 Device Selecting the boot deviceDefault switch positions Switch Default Function in default position Color Device Function LED indicatorsLists the PB926EJ-S LED indicators and their function LED Indicators LED ID Boot Monitor configuration Jtag connection Connecting Jtag debugging equipment USB debug port connection Example of MultiTrace and Jtag connection Connecting the Trace Port Analyzer Example of RealView ICE and RealView Trace Trace connector and adaptor board About using trace Power connectors Supplying power Boot Monitor commands Using the PB926EJ-S Boot Monitor and platform libraryRunning the Boot Monitor Command Action Lists the commands for the Boot MonitorBoot Monitor commands Boot Monitor Debug commands Lists the commands for the Debug subsystemBoot Monitor Configure commands Boot Monitor NOR flash commands Lists the commands for the NOR Flash subsystem Boot Monitor NOR flash commands CommandAction Rebuilding the Boot Monitor Getting Started For RealView DebuggerFrom the Debug menu → Include Commands Loading Boot Monitor into NOR flash Redirecting character output to hardware devices Rebuilding the platform library Building an application with the platform library Load region in flash Loading and running an application from NOR flash Using a boot script to run an image automatically ARM DUI Interrupts on Fpga onDMA on Hardware Description 1 ARM926EJ-S PXP Development Chip overview ARM926EJ-S PXP Development Chip ARM926EJ-S PXP Development Chip block diagram ARM926EJ-S r0p3 macrocell is a 32-bit cached processor with Embedded Trace Macrocell ETM provides signals for off-chipThis high-performance, low-power Vector Floating-Point VFP ARM926EJ-S CPU is a member of the ARM9 Thumb family. Memory controllers Synchronous serial port Configuration control Configuration switches Configuration signals from SYSCFGDATAx Configuration from the DEV Chip Reconfig pushbutton AHB bridges and the bus matrix Restoring the default configuration Simultaneous access Example of multiple masters AHB map Core APB and DMA APB map Memory devices Memory interface AHB monitor connection AHB monitor Shows the architecture of the Fpga on the PB926EJ-S Fpga For details on Fpga components, see Fpga configuration Fpga image 1 this is the image supplied with the board Localdone Globaldone Hardware Description Reset and reconfiguration logic Reset controller 11 PB926EJ-S reset logic Registers Peripherals Reset levelDefault values Memory 12 Reset signal sequence 13 Programmable reset level See -4 on page 3-29 for a description of the reset signals NSTATICCS1 if one of BOOTCSSEL10 is not b11 Memory aliasing at reset 14 Boot memory remap logic Name Function Reset signalsDescribes reset signals Reset signal descriptions NPORESET NPBRESETNPBSDCRECONFIG NPLLRESET Usbwakeup 15 Power-on reset and configuration timing Reset timing Power supply control 16 Standby switch and power-supply control Clock domains for the PB926EJ-S are shown in Figure Clock architecture ARM926EJ-S PXP Development Chip Clock domains for the PB926EJ-S are Controller interface to the Fpga Where it can be used as the CPU clock for low-power modeSignal nGLOBALCLKEN from Z50 on the Logic Tile indicates to Timing the Ethernet bus. HCLKM2 typically generated from ARM DUI 18 ARM926EJ-S PXP Development Chip internal multiplexors 1 ARM926EJ-S PXP Development Chip clocks Lists the clock signals Xtalclkext Default operationXtalclkdrv HCLKM2, HCLKS, PLLCLKEXT, GLOBALCLK, 19 Default clock sources and frequencies Example of changing the CPU and bus clock frequencies Xtalclkext Operating the AHB bridges in asynchronous mode 20 Clock sources for asynchronous AHB bridges HCLKSMF2F HCLKCTRL70HCLKM1M2F HCLKM2M2F HCLKM1 selection Default value of HCLKCTRL70 is 0xE0Hclkctrl signal HCLKM1 driven by Hclkctrl signal HCLKM2 driven by HCLKSL2S and HCLKSL2F from tile Hclkctrl signal Hclks driven byICS307 programmable clock generators Hclks selection Clcdclkext Selecting slow start Selecting the low-frequency clocks in power-saving mode Peripheral clocks XTALCLK/GLOBALCLK driven by RealView Logic Tile clocks10 Globalclk selection 22 Example of selecting a tile clock for the AHB S bridge Clock multiplexor logic 23 Clock multiplexors PCM 12 Audio system specificationCharacteristic Value Advanced Audio Codec Interface, Aaci No link Passive microphone on CODECMIC1 and CODECMIC2 Pin number Signal name Description 13 AC’97 audio debug signals on J45 Character LCD controller 25 Character display Clcdc interface 26 Display interface Chip Reference Manual for interface details Signal Description 14 Display interface signals DMA 27 DMA channels 15 DMA signals for external devices TPO+ , TPO Ethernet interfaceUSBETHD310 USBETHA82 About the Smsc LAN91C111 ARM DUI Gpio interface 29 Gpio block diagram 30 External and internal interrupt sources Interrupts Hardware Description Keyboard/Mouse Interface, KMI 31 KMI block diagram MMC or SD operation 17 MMC/SD interface signalsSignal Widebus mode SD only MMC mode default Memory Card Interface, MCI Card interface description Card insertion and removal 32 MMI interface MCIxDAT30 18 MMC signalsMCIPWRx CARDINx 33 PCI bridge PCI interface Sbscl 20 Serial bus signalsSerial bus interface 19 Serial bus addresses Slave address Slave device Bit Smart Card interface, SCI 35 SCI block diagram SCICLKOUTx SCIDATAIN0, SCICLKIN0, and SCIDETECT0 signals.SCICLKINx NSCICLKENx Synchronous Serial Port, SSP 36 SSP block diagram Name Description 22 SSP signal descriptions ARM DUI 37 Switch and LED interface User switches and LEDs Uart interface 38 UARTs block diagram SERxDTR a NDRVINEN0SERxTXD SERxRTS 23 Serial interface signal assignment USB interface 41 OTG243 block diagram Signal name Direction Description 24 USB interface signal assignment Test, configuration, and debug interfaces 42 Test and debug connectors, links, and LEDs Jtag and USB debug port support Jtag debug normal mode Jtag configuration mode Name Description Function Jtag signals25 Jtag related signals NCFGEN 25 Jtag related signals Name Description FunctionRtck Return TCK NRTCKEN Dbgack 43 Jtag connector signals 44 Jtag signal routing 45 RealView Logic Tile Jtag circuitry Embedded trace support ChipScope integrated logic analyzer MBX on Ethernet on Uart on Timers on 4KB Memory mapSdram Peripheral Location Interrupt a PIC Address Region SIC Size Memory map PIC Vectored Interrupt Controller PIC Uart 0 Interface Dev. chip PIC SIC PCI2GB ARM Data bus memory map Remapping of boot memory Configuration and initialization Simplified version of the remap logic is shown in -14 on Switch is ON, the corresponding Bootcssel signal is HighRemoving boot remapping and enabling Sdram at Enable Sdram at Programmer’s Reference Booting from NOR flash Booting from NOR flash Booting from static expansion memory Booting from static expansion memory Booting from AHB expansion Booting from AHB expansion memory Memory characteristics Memory banks Status and system control registers Name Address Accessa Reset Description Level Register map for system control registers Applycfgword active Describes the PB926EJ-S ID Register assignment Switch Register, SysswID Register, Sysid bit assignment Bits Access Description ID Register, Sysid Sysled LED Register, Sysled Shows the bit assignment of the registers Oscillator registers, SYSOSCx Describes the PB926EJ-S Lock Register bit assignment Lock Register, Syslock 6 100Hz Counter, SYS100HZ Configuration registers SYSCFGDATAx Bits Power-on Description Reset state Configuration register High PLL feedback see ARM926EJ-S PXP Development Chip clocks on CFGHCLKEXTDIVSEL20, clock control HIGH, then expansion memory is aliased to Flag and Nonvolatile Flag Set Registers Register name Address Access Reset by DescriptionFlag registers, SYSFLAGx and SYSNVFLAGx Flag and Nonvolatile Flag Registers PCI Control Register, Syspcictl Reset Control Register, Sysresetctl11 Reset level control Bits Access Description 13 Flash control Flash Control Register, SysflashClcd Control Register, Sysclcd 12 MCI control 14 Sysclcd register 14 Sysclcd 15 Sysclcdser register Boot Select Register, Sysbootcs14 2.2 inch LCD Control Register Sysclcdser 16 Boot configuration switches 16 Sysbootcs PnINTA LOW 16 24MHz Counter, SYS24MHZMiscellaneous System Control Register, Sysmisc SYS DMAPSR1 Name Address Access DescriptionDMA peripheral map registers, SYSDMAPSRx = USB a 19 shows the bit assignment of the registers Oscillator reset registers, SYSOSCRESETx Oscillator test registers, SYSTESTOSCx 20 Oscillator test registers Name Address Access Description DMA AHB monitor21 AHB monitor implementation Property Value 22 Aaci implementation PrimeCell Modifications 23 Modified Aaci PeriphID3 register Bit Access Description 24 Character LCD display implementation Character LCD display Charmask CharcomChardat Charrd Command Bit Description Pattern An overview of the commands available is listed in Table26 Character LCD display commands 27 Clcdc implementation Color LCD Controller, Clcdc VGA Display resolutions and display memory organization28 PrimeCell Clcdc register differences Chip 320x240 Svga 800x600 on Svga 36MHz, 0x2CACEpson 2.2in panel Qcif 10MHz, 0x2C2A Sanyo 3.8in panel Qvga 10MHz, 0x2C2A ARM DUI CLD20 CLD23CLD22 CLD21 32 Dmac implementation Direct Memory Access Controller and mapping registers 33 DMA channels DMA Requester 33 shows the DMA channel allocation 34 DMA mapping register format 21 SYSDMAP0-2 mapping register format 35 Ethernet implementation Ethernet Gpio General Purpose Input/Output, Gpio36 Gpio implementation Fpga Interrupt controllers37 VIC Primary Interrupt Controller implementation 38 SIC implementation Dmana Primary interrupt controller38 SIC implementation PropertyValue External interrupt from secondary controller 40 Interrupt signals to primary interrupt controllerBit Interrupt source a Description VICINTSOURCE31 Clcd GNDMBX Pwrfail Secondary interrupt controller Bit Interrupt Description Source 42 Interrupt signals to secondary interrupt controller Handling interrupts Example 4-1 Clearing and re-enabling SCI0 card out interrupt Example 4-3 Clearing and re-enabling SCI1 card out interrupt Example 4-2 Pseudo code for SIC SCI1 card out interrupt SCI1IMSC SCI1CARDOUTIM KMI Keyboard and Mouse Interface, KMI43 KMI implementation 44 MBX implementation 13 MBX Move video coprocessor 45 MCI implementation MultiMedia Card Interfaces, MCIx 46 Mpmc implementation MultiPort Memory Controller, MpmcRegister values SDRAM32M16BRCX32 47 Sdram register valuesAddress Register name Value Description Offset Mpmcclkout runs +0x144 MPMCDynamicRasCas2 Dmac PCI controller48 PCI controller implementation Control registers Address Name Access Description 50 PCI controller registers PCIIMAPx registersMap register formats are shown in -25 and -54 on 52 Pciselfid register format Pciselfid registerPciflags register Bits Description PCISMAPx registers 54 PCISMAPx register format PCI configurationMap register format is shown in -29 and Table Locating the self-config header table Address Configuration word function Default Offset Value 57 PCI configuration space header Configuring the PCI interface Limitations of the PCI interface Interrupt Acknowledge Ignored Not available 59 RTC implementation Real Time Clock, RTC Sbcontrolc 60 Serial bus implementation Property ValueSbcontrol Sbcontrols Dynamic expansion E2PROM 63 SCI implementation ARM PrimeCell Synchronous Serial Port Controller PL022 Register, Sysclcd on 65 Ssmc implementation Synchronous Static Memory Controller, Ssmc Address Name of Ssmc Value Description Register 67 Register values for Intel flash, async page mode 68 Register values for Samsung Sram SMBWSTBRDR4 SMBWSTOENR4SMBWSTWENR4 SMBCR4 See also Status and system control registers on System Controller 72 Timer implementation Timers 73 Uart implementation Uart PrimeCell Modifications Address Description 74 USB implementation 76 VFP9 implementation Vector Floating Point, VFP9 77 Watchdog implementation Watchdog 102 Signal Descriptions Synchronous Serial Port interface Signals associated with the SSP are shown in Table A-1Table A-1 SSP signal assignment Signal name Description Smart Card interface Pin Signal Description Signal Pin Signal name Table A-3 Signals on expansion connector SER1DTR a SER2DTR a SER3DTR a Table A-4 Serial plug signal assignmentPB926EJ-S provides four serial transceivers Top Bottom Figure A-5 shows the USB connectors Audio Codec interface Figure A-6 Audio connectors Figure A-7 MMC/SD card socket pin numbering MMC and SD flash card interface Table A-5 lists the signal assignments LCDID0 Table A-6 Clcd Interface board connector J18 Pin SignalClcd display interface Clle GND Clac Clcp Cllp Clfp Tsmiso LCDID3 Tsmosi LCDID4 Lcdxwr GND LCDSD0 Lcdxrd Lcdxcs ClpowerPWR3V5VSWITCH Vlcd Vddposswitch Vddnegswitch LCDID2 Figure A-9 Clcd Interface connector J18 VGA display interface Table A-7 VGA connector signals Pin Description Each data pin has an on-board 10KΩ pullup resistor to Figure A-11 Gpio connector Keyboard and mouse interface Table A-8 Mouse and keyboard port signal descriptionsKeyboard KMI0, J24 Mouse KMI1, J23 Pin Signal Function Pin Signals on the Ethernet cable are shown in Table A-9Table A-9 Ethernet signals Pin Signal Figure A-14 HDRX, HDRY, and Hdrz upper pin numbering RealView Logic Tile header connectors Table A-10 Hdrx J9 signals Platform signal Tile Pin Signal Hdrx signals Platform signal Tile Pin Signal Table A-10 Hdrx J9 signals HWRITEM2 SmcancelwaitHBUSREQM2 HCLKM1DRVL2S HDATAM210 HDATAM27HDATAM28 HDATAM29 Hdry signals Platform signal Tile signal Pin Signal Table A-11 Hdry J12 signals Hsels HRESPS0Hreadys Hmastlocks Ltclle HDATAS5Ltclcp HDATAS6 Hdrz Table A-12 Hdrz J8 signalsPlatform signal Tile signal Pin EXPSMADDR18 EXPSMADDR15EXPSMADDR16 EXPSMADDR17 Table A-12 Hdrz J8 signals Platform signal Tile signal Pin Dtdoin Dtdoout HCLKSRESF2L Clknegupout Ctdi BOOTCSSEL7 FpgaimageClknegdnin HCLKM1RESF2L Clkposupout EXPSMDATAS4 EXPSMDATAS1EXPSMDATAS2 EXPSMDATAS3 HPROTM13 EXPSMDATAS26HBURSTM10 EXPSMDATAS27 HDATAM111 HADDRM119HDATAM112 HADDRM120 Test and debug connections Figure A-15 Test points and debug connectors Overview of test points Test point Signal FunctionThis section contains the following subsections Jtag on page A-36 SPARE2 SCIDATAOUTTDD0Intclk REFCLK1 USB debug port Jtag Table A-14 Trace connector J14 Channel Pin Trace connector pinout Figure A-19 AMP Mictor connector Figure A-18 Embedded logic analyzer connector J33 Table A-15 AHB monitor connector J17 Channel Pin Table A-16 Fpga debug connector J39 Channel Pin Fpga debug connector pinout Specifications Table B-1 shows the PB926EJ-S electrical characteristics Electrical specificationBus interface characteristics Table B-2 Current requirements from DC System Typical Max Powered from DCPowered from J34 or PCI bus Current requirements Loading on supply voltage rails Clock rate restrictions Default clock rates for reliable operation are HTRANS10 , HSIZE20 , HBURST20 , and write data HRESETn inputAHB bus timing Hwrite , HTRANS10 , HSIZE20 , HBURST20 , Peripheral timing Memory timing Sspclk ClcdclkScirefclk Figure B-1 shows the mechanical outline of the PB926EJ-S Mechanical details ARM DUI Clcd Display and Adaptor Board Connectors on page C-15 About the Clcd display and adaptor board Figure C-1 Clcd adaptor board connectors bottom view Figure C-2 Small Clcd enclosure Figure C-3 Large Clcd enclosure Clcd Display and Adaptor Board Figure C-5 Clcd adaptor board connection Installing the Clcd display CXA-L0612VJL ConfigurationLCD power control TDK Switchedvddneg Fixedswitch Invio Switchedfixed Clpower SwitchedvddposSwitchedvddneg Figure C-6 Clcd buffer and power supply control links AUX21 Touchscreen controller interfaceTouchscreen interface architecture VBAT21 Touch Touchscreen controller programmer’s interface SSP and Tsci ConfigurationExample C-1 SSP to Tsci interface setup Example C-2 Configuring and reading the Tsci interface Table C-4 Clcd interface connector J2 Pin Signal ConnectorsInterface connector Table C-5 LCD prototyping connector J1 Signal Pin LCD prototyping connector Inverter prototyping connector Touchscreen prototyping connector AUX1 GND AUX2 VBAT1 VBAT2 5 A/D and keypad connectorTable C-8 A/D and keypad J13 Signal Pin Figure C-9 Clcd adaptor board mechanical layout Mechanical layout ARM DUI PCI Backplane and Enclosure Connecting the PB926EJ-S to the PCI enclosure PCI Backplane and Enclosure A socket, the socket is bypassed by an automatic switch Setting the backplane configuration switches Figure D-2 Multiple boards on PCI bus Connecting two PB926EJ-S boards Figure D-3 PCI backplane Backplane hardware CLK133ACTIVE Table D-1 LED indicatorsCLK33ACTIVE CLK66ACTIVE Test point Signal Description Table D-2 Configuration switchesSwitch Signal Description Table D-3 Power and reset switches Figure D-4 Jtag signal flow on the PCI backplane NPSON Power connectorTable D-5 ATX power connector Signal Pin 3V3 12V Channel Pin Logic analyzer connectorTable D-6 Mictor connector pinout SPARE4 Jtag connectorSignals on the Jtag connector J5 are shown in Figure D-6 Table D-6 Mictor connector pinout Channel Pin Memory Expansion Boards About memory expansion Figure E-1 Dynamic memory board block diagram Operation without expansion memory Memory board configuration Width Memory width selection on the static memory boardTable E-1 Memory width encoding Fitting a memory board Figure E-3 Memory board installation locations Eeprom contents Function Address Value Offset Table E-2 Chip Select information block Figure E-4 Chip select information block Address Contents Offset EXPnCS memory device string CS6 access time in 0.1ps LSB Address Contents Example contents DYCS3 memory size in bytes Expansion connector Connector pinout DATA3 DATA0DATA1 DATA2 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR0ADDR1 NCAS Table E-6 Static memory connector signalsPin No Signal NRAS Vddio a Table E-6 Static memory connector signals Pin No Signal NCS2 ADDR2NCS4 NCS3 ADDR18 ADDR15 NCS0 ADDR16ADDR17 NIRQ Figure E-6 Dynamic memory board layout RealView Logic Tile About the RealView Logic Tile Figure F-2 RealView Logic Tile fitted on PB926EJ-S Fitting a RealView Logic Tile Header connectors Figure F-3 HDRX, HDRY, and Hdrz upper pin numbering Variable I/O levels Figure F-4 RealView Logic Tile tristate for I/O RealView Logic Tile I/O RealView Logic Tile clocks Table F-1 RealView Logic Tile clock signals RealView Logic Tile ARM AHB M1 AHB buses used by the Fpga and RealView Logic Tiles Example RealView Logic Tile implementation AHB S Figure F-6 Bus signals for RealView Logic Tile and Fpga DnTRST pulse Reset Configuring the USB Debug Connection Installing the RealView Developer Suite Installing the RealView ICE Micro Edition driver Select Specify a location Installing the RealView ICE Micro Edition driver on Windows Configuring the USB Debug Connection Figure G-1 Nodes added to Connection Control window Changes to RealView Debugger Figure G-2 The Connection Control window Using the USB debug port to connect RealView Debugger Figure G-3 ARM926EJ-S PXP Development Chip detected Figure G-5 Error shown when no devices are detected Configuring the USB Debug Connection There are three groups of settings Using the Debug tab of the RealView Debugger Register pane Jtagclocktype Global PropertiesFalse True Device Properties Semihosting Properties ARM DUI MCI Uart AaciAHB Jtag LED ReconfigDMA KMI LCD SCI SYS ResetctlTCM Move Uart Xtalclkdrv SSP Uart