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Fujitsu Fujitsu SPARC64 V manual Instructionaccessexception

Models: Fujitsu SPARC64 V

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TABLE F-2MMU Trap Types, Causes, and Stored State Register Update Policy

					Registers Updated
				(Stored State in MMU)
				I-MMU		D-MMU
				Tag	D-SFSR,	Tag
Ref #Trap Name		Trap Cause	I-SFSR	Access	SFAR	Access	Trap Type

2.	instruction_access_exception	Several (see below)	X2	X			0816
3.	fast_data_access_MMU_miss	D-TLB miss			X3	X	6816–6B16
4.	data_access_exception	Several (see below)			X3	X1	3016
5.	fast_data_access_protection	Protection violation			X3	X	6C16-6F16
6.	privileged_action	Use of privileged ASI			X3		3716
7.	watchpoint	Watchpoint hit			X3		6116–6216
8.	mem_address_not_aligned,	Misaligned memory			(impl.		3516, 3616,
	*_mem_address_not_aligned	operation			dep		3816, 3916
					#237)
9.	instruction_access_error	Several (see below)	X2				0A16
10	data_access_error	Several (see below)			X3		3216

■X1: The contents of the context field of the D-MMU Tag Access Register are undefined after a data_access_exception.

■X2: I-SFSRis updated according to its update policy described in Section F.10.9

■X3: D-SFSRand D-SFARare updated according to the update policy described in Section F.10.9

The traps with Ref #1~8 in TABLE F-2conform to the specification defined in Section F.5 of Commonality.

The additional traps (Ref #9 and #10) are described below.

Ref 9: instruction_access_error — Signalled upon detection of at least one of the following errors.

■An uncorrectable error is detected upon an instruction fetch reference.

■A bus error response from the UPA bus is detected upon an instruction fetch reference.

■mITLB (sITLB and fITLB) multiple hits are detected in a mITLB lookup for an instruction reference.

■An fITLB entry parity error is detected in an fTLB lookup for an instruction reference.

Ref 10: data_access_error — Signalled upon the detection of at least one of the following errors.

■An uncorrectable error is detected upon an instruction operand access.

■A bus error response from the UPA bus is detected upon an operand access.

■mDTLB (sDTLB and fDTLB) multiple hits are detected in an mDTLB lookup for an operand access.

90 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

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Fujitsu Fujitsu SPARC64 V manual Instructionaccessexception

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Traps InstructionsImplementation Dependencies Sparc JPS1 Implementation-Dependent TrapsMemory Models Level-1 Instruction Cache L1I Cache Cache Organization 125 Cache TypesFatal Error Reset, REDstate, and errorstate 137 Reset TypesError Handling 149 Error Classification Asistchgerrorinfo Index UPA Programmer’s ModelGeneral References Page Fonts and Notational Conventions OverviewNavigating the SPARC64 V Implementation Supplement Microarchitecture for High Performance SPARC64 V processorHigh Integration High Reliability and High IntegrityExtended RAS interface to software Advanced RAS features for cachesAdvanced RAS features for the core Component Overview Asynchronous data error ADE trap for additional errorsSX-Unit Execution Unit EU Instruction Control Unit IU1Instruction Control Unit Major Blocks 2Execution Unit Major BlocksStorage Unit Major Blocks Storage Unit SU4Secondary Cache and External Access Unit Major Blocks Secondary Cache and External Access Unit SXUInstruction dispatch Synonym instruction initiation DefinitionsIssue-stalling Sync Synonym machine sync Page Architectural Overview Page Please refer to , Data Formats in Commonality Data FormatsPage Nonprivileged Registers RegistersFSRnonstandardfp NS Floating-Point State Register FSRFSRversion ver FSRfloating-pointtraptype fttTick Tick Register Privileged RegistersTrap State Tstate Register FSR ConformanceAncillary State Registers ASRs Version VER RegisterPerformance Control Register PCR ASR 1shows the values for the VER register for SPARC64Ovro OVFRegisters Referenced Through ASIs Accessibility as described above impl. dep. #250Performance Instrumentation Counter PIC Register ASR Dispatch Control Register DCR ASRVM70 PM70IU Deferred-Trap Queue Floating-Point Deferred-Trap Queue FQData Watchpoint Registers Instruction Trap RegisterData Prefetch InstructionsInstruction Execution Instruction Prefetch 1SPARC64 V Syncing Instructions Syncing InstructionsYes Instruction Formats and Fields2Instruction Fields Specific to SPARC64 Control-Transfer Instructions CTIs Instruction CategoriesCall and Jmpl Instructions Control transfer CTIImplementation-Dependent Instructions Floating-Point Operate FPop InstructionsInstruction Fetch Stages Processor PipelineBrhis Execution Stages Issue StagesCompletion Stages Execution Stages for Cache AccessPlease refer to .1 of Commonality TrapsProcessor States, Normal and Special Traps REDstate ErrorstateREDstate Trap Table REDstate Execution EnvironmentTrap Categories Reset TrapsDeferred Traps Uses of the Trap CategoriesTrap-Table Entry Addresses Trap ControlPIL Control Trap Type TTException and Interrupt Descriptions Trap ProcessingDetails of Supported Traps Sparc JPS1 Implementation-Dependent TrapsPage Sparc V9 Memory Model on Memory ModelsOverview Mode ControlSparc V9 Memory Model Synchronizing Instruction and Data MemoryRelease 1.0, 1 July Memory Models Page Table A-1Implementation-Specific Instructions Instruction Definitions SPARC64 V ExtensionsPage Block Load and Store Instructions VIS Invalid Valid Implementation-Dependent Instructions Call and LinkFormat Floating-Point Multiply-Add/SubtractPage Operation, and inexact, respectively Non-Trapping cexc When FSR.NS =Non-Trapping aexc When FSR.NS = Jump and Link Exceptions fpdisabledFormat 3 Ldda Load Quadword, Atomic PhysicalMemory Barrier Bits in the cmask Field Order Constraints Imposed by mmask Bits01816 Partial Store VISPrefetch Data Table A-7Prefetch Variants Read State RegisterTable A-7describes prefetch variants implemented in SPARC64 Store Barrier Write State RegisterDeprecated Instructions Page Traps Inhibiting Results Floating-Point Nonstandard ModeIeee Std 754-1985 Requirements for Fpexceptionother Exception ftt=unfinishedFPop UnfinishedFPop Boundary Conditions Denormalized number, eres is less than zeroGenerates an unfinishedFPop exception Table B-2unfinishedFPop Boundary Conditions Pessimistic ZeroPessimistic Overflow Operation Under FSR.NS =Table B-3Conditions for a Pessimistic Zero Table B-4Pessimistic Overflow ConditionsUnfinishedFPop4 Floating-Point Exceptional Conditions and ResultsYes and op2 Nv, dNaN Nonarithmetic Operations Under FSR.NS =Page Please refer to Section C.1 of Commonality Implementation DependenciesDefinition of an Implementation Dependency Implementation Dependency Categories Hardware CharacteristicsList of Implementation Dependencies Please refer to Section C.2 of CommonalityTable C-1SPARC64 V Implementation Dependencies Entering errorstate on implementation-dependent errors Reset trapErrorstate processor state Deferred trapsClean windows trap Data access FPU trapFlush instruction Floating-point underflow detectionMMU disabled prefetch behavior SIRenable control flagIMPDEPn instructions Unimplemented LDD trapUnimplemented values for PSTATE.MM Implicit ASI when TLCoherence and atomicity of memory operations Implementation-dependent memory modelTable C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 256 255257 258Please refer to Appendix D of Commonality Formal Specification of the Memory ModelsPage Instruction65 Opcode MapsPage Virtual Address Translation Memory Management UnitTable F-1Organization of SPARC64 V TLBs Translation Table Entry TTERelease 1.0, 1 July Chapter F Memory Management Unit TSB Pointer Formation TSB OrganizationTSB Pointer Formation TLB miss 64 16-67 Faults and TrapsInstructionaccessexception Reset, Disable, and REDstate Behavior Access Modes Supervisor read/write Accessing MMU RegistersInternal Registers and ASI operations Asimcntl Memory Control RegisterTable F-3MCNTL Field Description 10.4 I/D TLB Data In, Data Access, and Tag Read RegistersRMD JPS1TSBPPage TLB# Table F-4MMU TLB Data Access Address AssignmentKbyte page entry MMU TLB Tag Access RegisterMMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSR10.7 I/D TSB Extension Registers TSB Base RegistersEID Table F-5I-SFSRBit DescriptionSFSRBit Description FT60 Error DescriptionTable F-6describes the field encoding for ISFSR.FT Table F-8D-SFSRBit Description 1 Isfsr Update PolicyTable F-8D-SFSRBit Description 2 SFSRBit Description 3 Table F-9defines the encoding of the FT60 fieldFresh fault or miss3 MMU Synchronous Fault Status Register FT Fault Type FieldDsfsr Update Policy MMU Bypass Table F-10DSFSR Update PolicyKbytes Table F-11Bypass Attribute Bits on SPARC64Restriction of sTLB Entry Direct Replacement TLB Replacement PolicyAutomatic TLB Replacement Rule Page Please refer to Appendix G of Commonality Assembly Language SyntaxPage Please refer to Appendix H of Commonality Software ConsiderationsPage Please refer to Appendix I of Commonality Extending the Sparc V9 ArchitecturePage Please refer to Appendix K of Commonality Changes from Sparc V8 to SparcPage Please refer to Appendix J of Commonality Programming with the Memory ModelsPage SPARC64 V ASI Assignments 1 Address Space IdentifiersSPARC64 V ASI Assignments TBD SPARC64 V ASI Assignments 2SPARC64 V ASI Assignments 3 Special Memory Access ASIsPartial Store ASIs Block Load and Store ASIsHigh-Speed Lbsy Read Mechanism Barrier Assist for Parallel ProcessingInterface Definition Lbsy Control Register ASICLBSYR0, ASICLBSYR1 ASI RegistersHigh-Speed BST Write Mechanism Bstw Busy Status Register Asicbstwbusy Bstw Control Register ASICBSTW0, ASICBSTW1Barrier State Write ASIBSTW0, ASIBSTW1 Last Barrier Synchronization Status Read ASILBSYR0EF16 Read Write is ignoredCache Types Cache OrganizationLevel-1 Instruction Cache L1I Cache Table M-1L1I Cache CharacteristicsTable M-3L2 Cache Characteristics Table M-2L1D Cache CharacteristicsLevel-1 Data Cache L1D Cache Level-2 Unified Cache L2 CacheCache Control/Status Instructions Cache Coherency ProtocolsTable M-4Relationships Between Cache Coherency Protocols Table M-5L2 Cache Moesi StatesASIFLUSHL1I Flush Level-1 Instruction CacheTable M-6ASIL2CTRL Register Bits 3 L2 Diagnostics Tag ReadLevel-2 Cache Control Register ASIL2CTRL ASIL2DIAGTAGREADREG 4 L2 Diagnostics Tag Read RegistersPage Interrupt Dispatch Interrupt HandlingMembar Figure N-2is an example of the interrupt receive flow Interrupt ReceiveInterrupt-Related ASR Registers Interrupt Global RegistersInterrupt Vector Dispatch Register Interrupt Vector Dispatch Status RegisterReset Types Reset, REDstate, and errorstatePower-on Reset POR Appendix contains these sectionsSoftware-Initiated Reset SIR Watchdog Reset WDRExternally Initiated Reset XIR Figure O-1illustrates the processor state transition diagram REDstate and errorstatePA = 000007FFF000000016 CPU Fatal Error state Processor State after Reset and in REDstateInteger registers Floating Point registersMask dependent TBA6315Counter Table O-2ASR State after Reset and in REDstateASI Register State After Reset and in REDstate 1 Others ASI Register State After Reset and in REDstate 2ASI Register State After Reset and in REDstate 3 11011 Unchanged Operating Status Register OpsrTo be defined later Hardware Power-On Reset SequenceFirmware Initialization Sequence Page Fatal Error Error HandlingError Classification Instruction-Obstructing Error Errorstate Transition ErrorUrgent Error Urgent Error Independent of Instruction Execution Correctable Error CE, corrected by hardware Restrainable ErrorTraps for Urgent Errors Registers Related to Error Handling Action and Error ControlFollowing registers are related to the error handling Table P-1Registers Related to Error HandlingTable P-2Action Upon Detection of an Error 1 Summary of Actions Upon Error DetectionTable P-2summarizes what happens when an error is detected Deviation in SPARC64 Table P-2Action Upon Detection of an Error 2Ideal specification Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Marking for Cacheable Data ErrorTable P-4Format of Error-Marked Data Format of Error-Marking DataTable P-3Syndrome for Data Marked for Error Table P-5ERRORMARKID Bit Description Table P-6shows the Errormarkid set by the CPUTable P-7Error Marking on SPARC64 IV and SPARC64 Difference Between Error Marking on SPARC64 IVValue in ASIERRORCONTROL, as defined in Table P-9 Control of Error Action AsierrorcontrolTable P-8 Asieidr Bit Description RteueUgehandler WeakedTable P-10Format of Asistchgerrorinfo Bit Description Fatal Error and errorstate Transition Error4C16 Always 0 EeotherCurrent SPARC64 V implementation Fatal Error TypesTypes of errorstate Transition Errors Table P-11ASIUGESR Bit Description 1 Urgent ErrorIdeal specification not implemented Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Conditions that cause ADE trap Action of asyncdataerror ADE TrapTable P-11ASIUGESR Bit Description 4 Instend Priv Mugedae Mugeiae MugeiugeFollowing three sets of registers are updated Set the specific register settingFollowing actions are executed in this order State transitionInstruction End-Method at ADE Trap Update of ASIUGESR, as shown in Table P-13Upon completion of a Retry or Done instruction InstendExpected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap See Appendix F, Memory Management Unit, for details Instruction Access ErrorsData Access Errors Asiasyncfaultstatus Asiafsr Restrainable ErrorsCeincomed DGL1$U2$STLBUERAWL2$FILL UedstbetoUERAWL2$INSD Implementation Deviation SPARC64 V setsWAY ContentsSyndrome ASIASYNCFAULTADDRU2 register is described in Table P-17Contents of PABIT423 Expected Software Handling of Restrainable ErrorsPage Register Error Handling Excluding ASRs and ASI Registers Handling of Internal Register ErrorsTable P-18shows error handling for most registers Terminology used in Table P-18is defined as followsTable P-19shows the handling of ASR errors ASR Error HandlingTable P-19ASR Error Handling ADE trap, WError Protect ASI Register Error HandlingTerminology used in Table P-20is defined as follows Parity AlwaysError Detect Condition Correction Error TypeTable P-20Handling of ASI Register Errors Table P-20shows the handling of ASI register errorsTable P-20Handling of ASI Register Errors Handling of a Cache Tag Error Cache Error HandlingSPARC64 V Implementation and the Ideal Specification Error in D1 Cache Tag and I1 Cache TagError in U2 Unified Level 2 Cache Tag Correctable Error in D1 Cache Data Handling of an I1 Cache Data ErrorHandling of a D1 Cache Data Error Marked Uncorrectable Error in D1 Cache Data Correctable Error in U2 Cache Data Handling of a U2 Cache Data ErrorMarked Uncorrectable Error in U2 Cache Data Raw Uncorrectable Error in U2 Cache DataI1 Cache Way Reduction Automatic Way Reduction of I1 Cache, D1 Cache, and U2 CacheWay Reduction Condition U2 Cache Way Reduction D1 Cache Way ReductionHandling of TLB Entry Errors TLB Error HandlingError in TLB Entry Detected on Ldxa Instruction Access Table P-22Error Protection and Detection of TLB EntriesAutomatic Way Reduction of sTLB Handling of Extended UPA Address Bus Error Handling of Extended UPA Bus Interface ErrorHandling of Extended UPA Data Bus Error STLB Way ReductionCorrectable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Performance Monitor Overview Performance InstrumentationSample Pseudocodes Counter Clear/SetCounter Stop and Read Counter Event Selection and StartTable Q-1Events and Encoding of Performance Monitor Performance Monitor DescriptionEvents and Encoding of Performance Monitor Instruction StatisticsCounts the committed Floating Multiply-and-Add instructions Instruction Count instructioncountsTrap-Related Statistics Counts the occurrences of Tcc instructions MMU Event CountersCounts the occurrences of instruction uTLB misses Counts the occurrences of data uTLB missesCounts the occurrences of I1 cache misses Cache Event CountersCounts the occurrences of D1 cache misses Counts the total latency of I1 cache missesCounts L2 cache references by demand read access Counts the occurrences of L2 cache miss by demand accessCounts the number of Sinvreq packets received UPA Event CountersCounts the number of Scpireq packets received Counts the number of Scpbreq packets receivedBarrier-Assist ASI Read Count asirdbar Miscellaneous CountersPage Mapping of the CPU’s UPA Port Slave Area UPA Programmer’s ModelTable R-1shows the mapping of the CPU’s UPA port slave area Table R-1CPU’s UPA Port Slave Area MappingTable R-2UPA PortID Register Fields UPA PortID RegisterTable R-3UPA Config Register Description UPA Config RegisterUPA PortID Register Fields UpacapUPA Config Register Description UPCCAP2 PconMID UpccapPage SPARC64 V and UltraSPARC-III Differences 1 Summary of Differences between SPARC64 V and UltraSPARC-IIIUPA Table T-1SPARC64 V and UltraSPARC-III Differences 2Sfsr Table T-1SPARC64 V and UltraSPARC-III Differences 3Page Please refer to Bibliography in Commonality BibliographyGeneral References Page Auge IndexPage ASIINTRW133 Page DAE Error detection action155DGL1$L2$STLB error194 DGL1$U2$STLB error195 Dmmu On Jmpl instruction error53 update during MMU trap90Persistence38 ECCerror exception46, 153, 155Statistics monitoring206-207 FSR FQ17Immu Isfsr Update during MMU trap90PSO41 RMO41 Lddfa instruction80OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB UnimplementedFPop floating-point trap type70 UITLB10, 85, 90 uncorrectable error152Way reduction194 uDTLB10, 85