Fujitsu Fujitsu SPARC64 V manual Table F-5I-SFSRBit Description, Eid

The specification of bits 24:0 in the SPARC64 V SFSR conforms to the specification defined in Section F.10.9 in Commonality. Bits 63:25 in SPARC64 V SFSR are implementation dependent. TABLE F-5describes the I-SFSRbits, and TABLE F-5describes the D-SFSRbits.

TABLE F-5I-SFSRBit Description

Bits	Field Name	RW	Description
Data<63:62 >	TLB#	R/W	Faulty TLB# log. Recorded upon an mITLB error to identify the faulty TLB
			(fITLB: 002 or sITLB: 102). The priority of error logging for multiple error
			conditions (parity error and multiple-hit error) is as follows:
			fTLB parity	high
			sTLB
			sTLB multihit
			fTLB multihit	low
Data <59:49>	index	R/W	Faulty TLB index log. Recorded upon an mITLB error and is the index
			number for the faulty TLB. The priority of error logging for multiple error
			conditions (parity error and multiple-hit error) is as follows:
			fTLB parity	high
			sTLB parity
			sTLB multihit
			fTLB multihit	low
			The smallest index number is selected for multiple hits.
Data <46>	MK	R/W	Marked UE. On SPARC64 V, all uncorrectable errors are reported as
			marked, so this bit is always set whenever ISFSR.UE = 1.
			See Section P.2.4, Error Marking for Cacheable Data Error, on page 157 for
			details.
Data <45:32>	EID	R/W	Error mark ID. Valid for a marked UE.
			See Section P.2.4, Error Marking for Cacheable Data Error, on page 157 for
			ERROR_MARK_ID.
Data <31>	UE	R/W	Instruction error status; uncorrectable error. When UE = 1, an uncorrectable
			error in a fetched instruction word has been detected. Valid only for an
			instruction_access_error exception.
Data <30:29>	UPA<1:0>	R/W	UPA error status. Either a bus error response (UPA<1>) or a timeout
			response (UPA<0>) has been received from an instruction fetch transaction
			from UPA. Valid only for an instruction_access_error exception.
Data <27:26>	mITLB<1:0>	R/W	mITLB error status. Either a multiple-hit status (mITLB<1>) or a parity
			error status (mITLB<0>) has been encountered upon a mITLB lookup. Valid
			only for an instruction_access_error exception.
Data <25>	NC	R/W	Noncacheable reference. The reference that has invoked an exception is a
			noncacheable reference. Valid for an instruction_access_error exception
			caused by ISFSR.UE or ISFSR.UPA only. For other causes of the trap, the
			value is unknown.
Data <23:16>	ASI<7:0>	R/W	ASI. The 8-bit address space identifier applied to the reference that has
			invoked an exception. This field is valid for the exception in which the
			ISFSR.FV bit is set.

Arecorded ASI is 8016(ASI_PRIMARY) or 0416 (ASI_NUCLEUS) depending on the trap level (when TL > 0, the ASI is ASI_NUCLEUS.).

98 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002