Fujitsu Fujitsu SPARC64 V Privileged Registers, Tick Tick Register, Trap State Tstate Register

else if (<FPop commits with IEEE_754_exception>)

<set one bit in the CEXC field as supplied by FPU>; else if (<FPop commits with unfinished_FPop error>)

<no change>;

else if (<FPop commits with unimplemented_FPop error>) <no change>;

else

<no change>;

FSR Conformance

SPARC V9 allows the TEM, cexc, and aexc fields to be implemented in hardware in either of two ways (both of which comply with IEEE Std 754-1985). SPARC64 V follows case (1); that is, it implements all three fields in conformance with IEEE Std 754-1985. See FSR Conformance in Section 5.1.7 of Commonality for more information about other implementation methods.

5.1.9Tick (TICK) Register

SPARC64 V implements TICK.counter register as a 63-bit register (impl. dep. #105).

Implementation Note – On SPARC64 V, the counter part of the value returned when the TICK register is read is the value of TICK.counter when the RDTICK instruction is executed. The difference between the counter values read from the TICK register on two reads reflects the number of processor cycles executed between the executions of the RDTICK instructions, not their commits. In longer code sequences, the difference between this value and the value that would have been obtained when the instructions are committed would have been small.

5.2Privileged Registers

Please refer to Section 5.2 of Commonality for the description of privileged registers.

5.2.6Trap State (TSTATE) Register

SPARC64 V implements only bits 2:0 of the TSTATE.CWP field. Writes to bits 4 and 3 are ignored, and reads of these bits always return zeroes.

Release 1.0, 1 July 2002 F. Chapter 5 Registers 19