Fujitsu Fujitsu SPARC64 V IMPDEPn instructions, Unimplemented LDD trap, Unimplemented STD trap

Models: Fujitsu SPARC64 V

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TABLE C-1SPARC64 V Implementation Dependencies

(5 of 11)

 

 

 

Nbr

SPARC64 V Implementation Notes

Page

 

 

 

106

IMPDEPn instructions

49

 

SPARC64 V uses the IMPDEP2 opcode for the Multiply Add/Subtract

 

instructions. SPARC64 V also conforms to Sun’s specification for VIS-1 and

 

VIS-2.

 

107

Unimplemented LDD trap

 

SPARC64 V implements LDD in hardware.

 

108

Unimplemented STD trap

 

SPARC64 V implements STD in hardware.

 

109

LDDF_mem_address_not_aligned

 

If the address is word aligned but not doubleword aligned, SPARC64 V

 

generates the LDDF_mem_address_not_aligned exception. The trap handler

 

software emulates the instruction.

 

110

STDF_mem_address_not_aligned

 

If the address is word aligned but not doubleword aligned, SPARC64 V

 

generates the STDF_mem_address_not_aligned exception. The trap handler

 

software emulates the instruction.

 

111

LDQF_mem_address_not_aligned

 

SPARC64 V generates an illegal_instruction exception for all LDQFs. The

 

processor does not perform the check for fp_disabled. The trap handler

 

software emulates the instruction.

 

112

STQF_mem_address_not_aligned

 

SPARC64 V generates an illegal_instruction exception for all STQFs. The

 

processor does not perform the check for fp_disabled. The trap handler

 

software emulates the instruction.

 

113

Implemented memory models

42

 

SPARC64 V implements Total Store Order (TSO) for all the memory models

 

specified in PSTATE.MM. See Chapter 8, Memory Models, for details.

114

RED_state trap vector address (RSTVaddr)

36

 

RSTVaddr is a constant in SPARC64 V, where:

 

 

VA=FFFF FFFF F000 000016 and

 

 

PA=07FF F000 000016

 

115

RED_state processor state

36

 

See RED_state on page 36 for details of implementation-specific actions in

 

RED_state.

 

116

SIR_enable control flag

 

See Section A.60 SIR in Commonality for details.

 

117

MMU disabled prefetch behavior

91

Prefetch and nonfaulting Load always succeed when the MMU is disabled.

118 Identifying I/O locations

This dependency is beyond the scope of this publication. It should be defined in a system that uses SPARC64 V.

74 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

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Fujitsu Fujitsu SPARC64 V IMPDEPn instructions, Unimplemented LDD trap, Unimplemented STD trap, Implemented memory models