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Fujitsu Fujitsu SPARC64 V manual 10.4 I/D TLB Data In, Data Access, and Tag Read Registers, Rmd

Models: Fujitsu SPARC64 V

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TABLE F-3MCNTL Field Description

Bits	Field Name	RW	Description

Data <16>	NC_Cache	R/W	Force instruction caching. When set, the instruction lines fetched from a
			noncacheable area are cached in the instruction cache. The NC_Cache
			has no effect on operand references. If MCNTL.NC_Cache = 1, the CPU
			fetches a noncacheable line in four consecutive 16-byte fetches and stores
			the entire 64 bytes in the I-Cache. NC_Cache is provided for use by OBP,
			and OBP should clear the bit before exiting.
			A write to ASI_FLUSH_L1I must be performed before
			MCNTL.NC_CACHE = 0 is set. Otherwise, noncacheable instructions may
			remain on the L1 cache.
Data <15>	fw_fITLB	R/W	Force write to fITLB. This is the mITLB version of fTLB force write.
			When fw_fITLB = 1, a TTE write to mITLB through ITLB Data In
			Register is directed to fITLB. fw_fITLB is provided for use by OBP to
			register the TTEs that map the address translations themselves into
			fDTLB.
Data <13:12>	RMD	R	TLB RAM MODE. Handling of 4-Mbyte page entry is indicated on this
			fileld.
			00: 4-Mbyte page entry is stored in fully associative TLB.
			01: reserved.
			10: 4-Mbyte page entry is stored in 1024-entry, 2-way set associative
			TLB.
			11: 4-Mbyte page entry is stored in 512-entry, 2-way set associative
			TLB.
			This field is read-only. Writes to this field is ignored.
Data <14>	fw_fDTLB	R/W	Force write to fDTLB. When fw_fDTLB = 1, a TTE write to mDTLB
			through DTLB Data In Register is directed to fDTLB. fw_fDTLB is
			provided for use by OBP to register the TTEs that map the address
			translations themselves into fDTLB.
Data <8>	JPS1_TSBP	R/W	TSB-pointer context-hashing enable. When JPS1_TSBP = 0, SPARC64 V
			does not apply the context-ID hashing for 8-Kbyte or 64-Kbyte TSB
			pointer generation. The pointer generation strategy is compatible with
			UltraSPARC. When JPS1_TSBP = 1, SPARC64 V is in JPS1_TSBP mode,
			meaning that the CPU applies the context-ID hashing to generate an 8-
			Kbyte or 64-Kbyte page TSB pointer.

F.10.4 I/D TLB Data In, Data Access, and Tag Read Registers

IMPL. DEP. #234: The replacement algorithm of a TLB entry is implementation dependent in JPS1.

Release 1.0, 1 July 2002

F. Chapter F Memory Management Unit 93

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Fujitsu Fujitsu SPARC64 V 10.4 I/D TLB Data In, Data Access, and Tag Read Registers, Table F-3MCNTL Field Description, Rmd

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Instructions TrapsImplementation Dependencies Sparc JPS1 Implementation-Dependent TrapsMemory Models Cache Organization 125 Cache Types Level-1 Instruction Cache L1I CacheFatal Error Reset, REDstate, and errorstate 137 Reset TypesError Handling 149 Error Classification Asistchgerrorinfo Index UPA Programmer’s ModelGeneral References Page Fonts and Notational Conventions OverviewNavigating the SPARC64 V Implementation Supplement SPARC64 V processor Microarchitecture for High PerformanceHigh Integration High Reliability and High IntegrityExtended RAS interface to software Advanced RAS features for cachesAdvanced RAS features for the core Asynchronous data error ADE trap for additional errors Component OverviewSX-Unit Instruction Control Unit IU Execution Unit EU1Instruction Control Unit Major Blocks 2Execution Unit Major BlocksStorage Unit SU Storage Unit Major BlocksSecondary Cache and External Access Unit SXU 4Secondary Cache and External Access Unit Major BlocksDefinitions Instruction dispatch Synonym instruction initiationIssue-stalling Sync Synonym machine sync Page Architectural Overview Page Data Formats Please refer to , Data Formats in CommonalityPage Registers Nonprivileged RegistersFloating-Point State Register FSR FSRnonstandardfp NSFSRversion ver FSRfloating-pointtraptype fttPrivileged Registers Tick Tick RegisterTrap State Tstate Register FSR ConformanceVersion VER Register Ancillary State Registers ASRsPerformance Control Register PCR ASR 1shows the values for the VER register for SPARC64OVF OvroAccessibility as described above impl. dep. #250 Registers Referenced Through ASIsPerformance Instrumentation Counter PIC Register ASR Dispatch Control Register DCR ASRPM70 VM70Floating-Point Deferred-Trap Queue FQ IU Deferred-Trap QueueData Watchpoint Registers Instruction Trap RegisterData Prefetch InstructionsInstruction Execution Instruction Prefetch Syncing Instructions 1SPARC64 V Syncing InstructionsYes Instruction Formats and Fields2Instruction Fields Specific to SPARC64 Instruction Categories Control-Transfer Instructions CTIsCall and Jmpl Instructions Control transfer CTIFloating-Point Operate FPop Instructions Implementation-Dependent InstructionsProcessor Pipeline Instruction Fetch StagesBrhis Issue Stages Execution StagesExecution Stages for Cache Access Completion StagesPlease refer to .1 of Commonality TrapsProcessor States, Normal and Special Traps Errorstate REDstateREDstate Trap Table REDstate Execution EnvironmentReset Traps Trap CategoriesDeferred Traps Uses of the Trap CategoriesTrap Control Trap-Table Entry AddressesPIL Control Trap Type TTTrap Processing Exception and Interrupt DescriptionsDetails of Supported Traps Sparc JPS1 Implementation-Dependent TrapsPage Memory Models Sparc V9 Memory Model onMode Control OverviewSparc V9 Memory Model Synchronizing Instruction and Data MemoryRelease 1.0, 1 July Memory Models Page Instruction Definitions SPARC64 V Extensions Table A-1Implementation-Specific InstructionsPage Block Load and Store Instructions VIS Invalid Valid Call and Link Implementation-Dependent InstructionsFloating-Point Multiply-Add/Subtract FormatPage Operation, and inexact, respectively Non-Trapping cexc When FSR.NS =Non-Trapping aexc When FSR.NS = Exceptions fpdisabled Jump and LinkLoad Quadword, Atomic Physical Format 3 LddaMemory Barrier Order Constraints Imposed by mmask Bits Bits in the cmask Field01816 Partial Store VISPrefetch Data Table A-7Prefetch Variants Read State RegisterTable A-7describes prefetch variants implemented in SPARC64 Store Barrier Write State RegisterDeprecated Instructions Page Traps Inhibiting Results Floating-Point Nonstandard ModeIeee Std 754-1985 Requirements for Fpexceptionother Exception ftt=unfinishedFPop UnfinishedFPop Boundary Conditions Denormalized number, eres is less than zeroGenerates an unfinishedFPop exception Pessimistic Zero Table B-2unfinishedFPop Boundary ConditionsOperation Under FSR.NS = Pessimistic OverflowTable B-3Conditions for a Pessimistic Zero Table B-4Pessimistic Overflow ConditionsFloating-Point Exceptional Conditions and Results UnfinishedFPop4Nonarithmetic Operations Under FSR.NS = Yes and op2 Nv, dNaNPage Please refer to Section C.1 of Commonality Implementation DependenciesDefinition of an Implementation Dependency Hardware Characteristics Implementation Dependency CategoriesList of Implementation Dependencies Please refer to Section C.2 of CommonalityTable C-1SPARC64 V Implementation Dependencies Reset trap Entering errorstate on implementation-dependent errorsErrorstate processor state Deferred trapsData access FPU trap Clean windows trapFlush instruction Floating-point underflow detectionSIRenable control flag MMU disabled prefetch behaviorIMPDEPn instructions Unimplemented LDD trapImplicit ASI when TL Unimplemented values for PSTATE.MMCoherence and atomicity of memory operations Implementation-dependent memory modelTable C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 255 256257 258Formal Specification of the Memory Models Please refer to Appendix D of CommonalityPage Opcode Maps Instruction65Page Memory Management Unit Virtual Address TranslationTranslation Table Entry TTE Table F-1Organization of SPARC64 V TLBsRelease 1.0, 1 July Chapter F Memory Management Unit TSB Pointer Formation TSB OrganizationTSB Pointer Formation Faults and Traps TLB miss 64 16-67Instructionaccessexception Reset, Disable, and REDstate Behavior Accessing MMU Registers Access Modes Supervisor read/writeInternal Registers and ASI operations Asimcntl Memory Control Register10.4 I/D TLB Data In, Data Access, and Tag Read Registers Table F-3MCNTL Field DescriptionRMD JPS1TSBPPage Table F-4MMU TLB Data Access Address Assignment TLB#MMU TLB Tag Access Register Kbyte page entry10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSR MMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR10.7 I/D TSB Extension Registers TSB Base RegistersTable F-5I-SFSRBit Description EIDSFSRBit Description FT60 Error DescriptionTable F-6describes the field encoding for ISFSR.FT Isfsr Update Policy Table F-8D-SFSRBit Description 1Table F-8D-SFSRBit Description 2 Table F-9defines the encoding of the FT60 field SFSRBit Description 3Fresh fault or miss3 MMU Synchronous Fault Status Register FT Fault Type FieldDsfsr Update Policy Table F-10DSFSR Update Policy MMU BypassKbytes Table F-11Bypass Attribute Bits on SPARC64Restriction of sTLB Entry Direct Replacement TLB Replacement PolicyAutomatic TLB Replacement Rule Page Assembly Language Syntax Please refer to Appendix G of CommonalityPage Software Considerations Please refer to Appendix H of CommonalityPage Extending the Sparc V9 Architecture Please refer to Appendix I of CommonalityPage Changes from Sparc V8 to Sparc Please refer to Appendix K of CommonalityPage Programming with the Memory Models Please refer to Appendix J of CommonalityPage SPARC64 V ASI Assignments 1 Address Space IdentifiersSPARC64 V ASI Assignments SPARC64 V ASI Assignments 2 TBDSpecial Memory Access ASIs SPARC64 V ASI Assignments 3Block Load and Store ASIs Partial Store ASIsHigh-Speed Lbsy Read Mechanism Barrier Assist for Parallel ProcessingInterface Definition Lbsy Control Register ASICLBSYR0, ASICLBSYR1 ASI RegistersHigh-Speed BST Write Mechanism Bstw Control Register ASICBSTW0, ASICBSTW1 Bstw Busy Status Register AsicbstwbusyLast Barrier Synchronization Status Read ASILBSYR0 Barrier State Write ASIBSTW0, ASIBSTW1EF16 Read Write is ignoredCache Organization Cache TypesTable M-1L1I Cache Characteristics Level-1 Instruction Cache L1I CacheTable M-2L1D Cache Characteristics Table M-3L2 Cache CharacteristicsLevel-1 Data Cache L1D Cache Level-2 Unified Cache L2 CacheCache Coherency Protocols Cache Control/Status InstructionsTable M-4Relationships Between Cache Coherency Protocols Table M-5L2 Cache Moesi StatesFlush Level-1 Instruction Cache ASIFLUSHL1ITable M-6ASIL2CTRL Register Bits 3 L2 Diagnostics Tag ReadLevel-2 Cache Control Register ASIL2CTRL 4 L2 Diagnostics Tag Read Registers ASIL2DIAGTAGREADREGPage Interrupt Handling Interrupt DispatchMembar Interrupt Receive Figure N-2is an example of the interrupt receive flowInterrupt Global Registers Interrupt-Related ASR RegistersInterrupt Vector Dispatch Register Interrupt Vector Dispatch Status RegisterReset, REDstate, and errorstate Reset TypesPower-on Reset POR Appendix contains these sectionsSoftware-Initiated Reset SIR Watchdog Reset WDRExternally Initiated Reset XIR REDstate and errorstate Figure O-1illustrates the processor state transition diagramPA = 000007FFF000000016 Processor State after Reset and in REDstate CPU Fatal Error stateInteger registers Floating Point registersTBA6315 Mask dependentCounter Table O-2ASR State after Reset and in REDstateASI Register State After Reset and in REDstate 1 ASI Register State After Reset and in REDstate 2 OthersASI Register State After Reset and in REDstate 3 Operating Status Register Opsr 11011 UnchangedTo be defined later Hardware Power-On Reset SequenceFirmware Initialization Sequence Page Fatal Error Error HandlingError Classification Instruction-Obstructing Error Errorstate Transition ErrorUrgent Error Urgent Error Independent of Instruction Execution Correctable Error CE, corrected by hardware Restrainable ErrorTraps for Urgent Errors Action and Error Control Registers Related to Error HandlingFollowing registers are related to the error handling Table P-1Registers Related to Error HandlingTable P-2Action Upon Detection of an Error 1 Summary of Actions Upon Error DetectionTable P-2summarizes what happens when an error is detected Deviation in SPARC64 Table P-2Action Upon Detection of an Error 2Ideal specification Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Error Marking for Cacheable DataTable P-4Format of Error-Marked Data Format of Error-Marking DataTable P-3Syndrome for Data Marked for Error Table P-6shows the Errormarkid set by the CPU Table P-5ERRORMARKID Bit DescriptionDifference Between Error Marking on SPARC64 IV Table P-7Error Marking on SPARC64 IV and SPARC64Control of Error Action Asierrorcontrol Value in ASIERRORCONTROL, as defined in Table P-9Table P-8 Asieidr Bit Description RteueWeaked UgehandlerFatal Error and errorstate Transition Error Table P-10Format of Asistchgerrorinfo Bit Description4C16 Always 0 EeotherCurrent SPARC64 V implementation Fatal Error TypesTypes of errorstate Transition Errors Table P-11ASIUGESR Bit Description 1 Urgent ErrorIdeal specification not implemented Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Action of asyncdataerror ADE Trap Conditions that cause ADE trapTable P-11ASIUGESR Bit Description 4 Instend Priv Mugedae Mugeiae MugeiugeSet the specific register setting Following three sets of registers are updatedFollowing actions are executed in this order State transitionUpdate of ASIUGESR, as shown in Table P-13 Instruction End-Method at ADE TrapUpon completion of a Retry or Done instruction InstendExpected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap See Appendix F, Memory Management Unit, for details Instruction Access ErrorsData Access Errors Restrainable Errors Asiasyncfaultstatus AsiafsrDGL1$U2$STLB CeincomedUedstbeto UERAWL2$FILLUERAWL2$INSD Implementation Deviation SPARC64 V setsContents WAYASIASYNCFAULTADDRU2 register is described in Table P-17 SyndromeExpected Software Handling of Restrainable Errors Contents of PABIT423Page Handling of Internal Register Errors Register Error Handling Excluding ASRs and ASI RegistersTable P-18shows error handling for most registers Terminology used in Table P-18is defined as followsASR Error Handling Table P-19shows the handling of ASR errorsTable P-19ASR Error Handling ADE trap, WASI Register Error Handling Error ProtectTerminology used in Table P-20is defined as follows Parity AlwaysError Detect Condition Error Type CorrectionTable P-20shows the handling of ASI register errors Table P-20Handling of ASI Register ErrorsTable P-20Handling of ASI Register Errors Cache Error Handling Handling of a Cache Tag ErrorSPARC64 V Implementation and the Ideal Specification Error in D1 Cache Tag and I1 Cache TagError in U2 Unified Level 2 Cache Tag Correctable Error in D1 Cache Data Handling of an I1 Cache Data ErrorHandling of a D1 Cache Data Error Marked Uncorrectable Error in D1 Cache Data Handling of a U2 Cache Data Error Correctable Error in U2 Cache DataMarked Uncorrectable Error in U2 Cache Data Raw Uncorrectable Error in U2 Cache DataI1 Cache Way Reduction Automatic Way Reduction of I1 Cache, D1 Cache, and U2 CacheWay Reduction Condition D1 Cache Way Reduction U2 Cache Way ReductionTLB Error Handling Handling of TLB Entry ErrorsError in TLB Entry Detected on Ldxa Instruction Access Table P-22Error Protection and Detection of TLB EntriesAutomatic Way Reduction of sTLB Handling of Extended UPA Bus Interface Error Handling of Extended UPA Address Bus ErrorHandling of Extended UPA Data Bus Error STLB Way ReductionCorrectable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Performance Instrumentation Performance Monitor OverviewSample Pseudocodes Counter Clear/SetCounter Event Selection and Start Counter Stop and ReadPerformance Monitor Description Table Q-1Events and Encoding of Performance MonitorInstruction Statistics Events and Encoding of Performance MonitorInstruction Count instructioncounts Counts the committed Floating Multiply-and-Add instructionsTrap-Related Statistics MMU Event Counters Counts the occurrences of Tcc instructionsCounts the occurrences of instruction uTLB misses Counts the occurrences of data uTLB missesCache Event Counters Counts the occurrences of I1 cache missesCounts the occurrences of D1 cache misses Counts the total latency of I1 cache missesCounts the occurrences of L2 cache miss by demand access Counts L2 cache references by demand read accessUPA Event Counters Counts the number of Sinvreq packets receivedCounts the number of Scpireq packets received Counts the number of Scpbreq packets receivedMiscellaneous Counters Barrier-Assist ASI Read Count asirdbarPage UPA Programmer’s Model Mapping of the CPU’s UPA Port Slave AreaTable R-1shows the mapping of the CPU’s UPA port slave area Table R-1CPU’s UPA Port Slave Area MappingUPA PortID Register Table R-2UPA PortID Register FieldsUPA Config Register Table R-3UPA Config Register DescriptionUPA PortID Register Fields UpacapUPA Config Register Description Pcon UPCCAP2MID UpccapPage Summary of Differences between SPARC64 V and UltraSPARC-III SPARC64 V and UltraSPARC-III Differences 1Table T-1SPARC64 V and UltraSPARC-III Differences 2 UPATable T-1SPARC64 V and UltraSPARC-III Differences 3 SfsrPage Please refer to Bibliography in Commonality BibliographyGeneral References Page Index AugePage ASIINTRW133 Page Error detection action155 DAEDGL1$L2$STLB error194 DGL1$U2$STLB error195 On Jmpl instruction error53 update during MMU trap90 DmmuECCerror exception46, 153, 155 Persistence38Statistics monitoring206-207 FQ17 FSRImmu Update during MMU trap90 IsfsrLddfa instruction80 PSO41 RMO41OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB UnimplementedFPop floating-point trap type70 UITLB10, 85, 90 uncorrectable error152Way reduction194 uDTLB10, 85