Fujitsu Fujitsu SPARC64 V manual Table P-2Action Upon Detection of an Error 2, Ideal specification

TABLE P-2Action Upon Detection of an Error (2 of 4)

		Error State Transition
	Fatal Error (FE)	Error (EE)	Urgent Error (UGE)	Restrainable Error (RE)
Action upon the	1. CPU enters	1. CPU enters	Detection of I_UGE	Ideal specification
error detection	CPU fatal	error_state.	When	1. The error detection is kept
	state.	2. Watchdog reset	ASI_ECR.UGE_HANDLER = 0,	pending in one bit of
	2. CPU informs	(WDR) is caused	a single-ADEtrap is caused.	ASI_AFSR.
	the system of	on the CPU.	Otherwise, when	2. When the trap condition
	fatal error		ASI_ECR.UGE_HANDLER = 1,	for the pending error
	occurrence.		a multiple-ADEtrap is caused.	detection is enabled, the
	3. The FATAL		Detection of A_UGE	ECC_error exception is
	reset (which is			generated.
			When the trap is enabled, a
	a form of POR			Deviation in SPARC64 V
			single-ADEtrap is caused.
	reset) is issued			An ECC_error trap can occur
			When the trap is disabled, the
	to the whole
			trap condition is kept pending	even though ASI_AFSR
	system.
			in hardware.	does not indicate any
	4. POR reset is
				detected error(s)
			Detection of IAE
	caused to all
				corresponding to any trap-
	CPUs in the		When
				enable bit (RTE_UE or
	system.		ASI_ECR.UGE_HANDLER = 0,
				RTE_CEDG) set to 1 in
			an IAE trap is caused. Other-	ASI_ECR, in the following
			wise, a multiple-ADEtrap is
				cases:
			caused.
				1. A pending detected error
			Detection of DAE
				is erased from ASI_ASFR
			When	(by writing 1 to
			ASI_ECR.UGE_HANDLER = 0,	ASI_AFSR) after the error
			a DAE trap is caused. Other-	is detected but before the
			wise, a multiple-ADEtrap is	ECC_error trap is
			caused.	generated.
				2. A pending CE or DG is
				erased by writing 1 to
				ASI_AFSR after the
				ECC_error trap is caused
				by the UE error detection.
				3. A pending UE is erased by
				writing 1 to ASI_AFSR
				after the ECC_error trap is
				caused by CE or DG
				detection.
				Privileged software should
				ignore an ECC_error trap
				when the AFSR contains no
				errors corresponding to
				those enabled in ASI_ECR
				to cause a trap.
Priority of	1 — CPU fatal	2 — error_state	3 — ADE trap	6 — ECC_error trap
action when	state		4 — DAE trap
multiple types			5 — IAE trap
of errors are
simultaneously
detected

Release 1.0, 1 July 2002 F. Chapter P Error Handling 155