Fujitsu Fujitsu SPARC64 V manual MMU Bypass, Kbytes, Table F-10DSFSR Update Policy

TABLE F-10DSFSR Update Policy

	Field	TLB#,	FV	OW	W, PR,	FT	TM	ASI	UE, UPA,	DSFAR
		index			NF, CT1				mDTLB, NC2, E2
Miss on fault/exception		K	1	K	K	K	1	K	K	K
Miss on miss		K	K	K	U	K	1	K	K	K

1.The value of DSFSR.CT is 11 when the ASI is not a translating ASI. The value 11 is recorded in DSFSR.CT for an illegal value in ASI (0016–0316, 1216–1316, 1616–1716, 1A16–1B16, 1E16–2316, 2D16–2F16, or 3516–3B16).

2.Valid only for the data_access_error caused by DSFSR.UE or DSFSR.UPA.

3.Types: 0 – logic 0; 1 – logic 1; V – Valid field to be updated; “—” – not a valid field

4.Memory reference instruction only.

5.Updated when mDTLB is signified.

6.Types: 0 – logic 0; 1 – logic 1; V– Valid field to be updated; “—” – not a valid field

7.Fault/exception on miss means the miss happened first, then a fault/exception was encountered before soft- ware had a chance to clear the DSFSR register.

F.11 MMU Bypass

On SPARC64 V, two additional ASIs are supported as DMMU bypass accesses: ASI_ATOMIC_QUAD_LDD_PHYS (ASI 3416) and ASI_ATOMIC_QUAD_LDD_PHYS_LITTLE (ASI 3C16)

TABLE F-11shows the bypass attribute bits on SPARC64 V. The first four rows conform to the bypass attribute bits defined in TABLE F-15 of Commonality.

TABLE F-11Bypass Attribute Bits on SPARC64 V

ASI	ASI					Attribute Bits
NAME	VALUE	CP	IE	CV	E	P	W	NFO	Size
ASI_PHYS_USE_EC	1416	1	0	0	0	0	1	0	8 Kbytes
ASI_PHYS_USE_EC_LITTLE	1C16
ASI_PHYS_BYPASS_EC_WITH_EBIT	1516	0	0	0	1	0	1	0	8 Kbytes
ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE	1D16
ASI_ATOMIC_QUAD_LDD_PHYS	3416	0	0	1	0	0	0	0	8 Kbytes
ASI_ATOMIC_QUAD_LDD_PHYS_LITTLE	3C16

104 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002