PA = 000007FFF000000016 | Fujitsu Fujitsu SPARC64 V instruction

O.2.1 RED_state

Once the processor enters RED_state for any reason except when a power-on reset (POR) is performed, the software should not attempt to return to execute_state; if software attempts a return, then the state of the processor is unpredictable.

When the processor processes a reset or a trap that enters RED_state, it takes a trap at an offset relative to the RED_state trap table (RSTVaddr); in the processor this is at virtual address VA = FFFFFFFFF000000016 and physical address

PA = 000007FFF000000016.

The following list further describes the processor behavior upon entry into

RED_state, and during RED_state:

■Whenever the processor enters RED_state, all fetch buffers are invalidated.

■When the processor enters RED_state because of a trap or reset, the DCUCR register is updated by hardware to disable several hardware features. Software must set these bits when required (for example, when the processor exits from

RED_state).

■When the processor enters RED_state not because of a trap or reset (that is, when the PSTATE.RED bit has been set by WRPR), these register bits are unchanged—unlike the case above. The only side effect is the disabling of the instruction MMU.

■When the processor is in RED_state, it behaves as if the IMMU is disabled (DCUCR.IM is clear), regardless of the actual values in the respective control register.

■Caches continue to snoop and maintain coherence while the processor is in

RED_state.

O.2.2 error_state

The processor enters error_state when a trap occurs and TL = MAXTL (5) or when the second watchdog timeout has occurred.

On the normal setting, the processor immediately generates a watchdog reset trap (WDR) and transitions to RED_state. Otherwise, the OPSR (Operating Status Register) specifies the stop on error_state, that is, the processor does not generate a watchdog reset after error_state transition and remains in the error_state.

140 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Image 151

Fujitsu Fujitsu SPARC64 V manual PA = 000007FFF000000016

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Traps Instructions Memory Models Sparc JPS1 Implementation-Dependent TrapsImplementation Dependencies Level-1 Instruction Cache L1I Cache Cache Organization 125 Cache Types Error Handling 149 Error Classification Reset, REDstate, and errorstate 137 Reset TypesFatal Error Asistchgerrorinfo General References UPA Programmer’s ModelIndex Page Navigating the SPARC64 V Implementation Supplement OverviewFonts and Notational Conventions High Reliability and High Integrity SPARC64 V processorMicroarchitecture for High Performance High Integration Advanced RAS features for the core Advanced RAS features for cachesExtended RAS interface to software Component Overview Asynchronous data error ADE trap for additional errors SX-Unit 2Execution Unit Major Blocks Instruction Control Unit IUExecution Unit EU 1Instruction Control Unit Major Blocks Storage Unit Major Blocks Storage Unit SU 4Secondary Cache and External Access Unit Major Blocks Secondary Cache and External Access Unit SXU Instruction dispatch Synonym instruction initiation Definitions Issue-stalling Sync Synonym machine sync Page Architectural Overview Page Please refer to , Data Formats in Commonality Data FormatsPage Nonprivileged Registers Registers FSRfloating-pointtraptype ftt Floating-Point State Register FSRFSRnonstandardfp NS FSRversion ver FSR Conformance Privileged RegistersTick Tick Register Trap State Tstate Register 1shows the values for the VER register for SPARC64 Version VER RegisterAncillary State Registers ASRs Performance Control Register PCR ASR Ovro OVF Dispatch Control Register DCR ASR Accessibility as described above impl. dep. #250Registers Referenced Through ASIs Performance Instrumentation Counter PIC Register ASR VM70 PM70 Instruction Trap Register Floating-Point Deferred-Trap Queue FQIU Deferred-Trap Queue Data Watchpoint Registers Instruction Execution InstructionsData Prefetch Instruction Prefetch 1SPARC64 V Syncing Instructions Syncing Instructions 2Instruction Fields Specific to SPARC64 Instruction Formats and FieldsYes Control transfer CTI Instruction CategoriesControl-Transfer Instructions CTIs Call and Jmpl Instructions Implementation-Dependent Instructions Floating-Point Operate FPop Instructions Instruction Fetch Stages Processor Pipeline Brhis Execution Stages Issue Stages Completion Stages Execution Stages for Cache Access Processor States, Normal and Special Traps TrapsPlease refer to .1 of Commonality REDstate Execution Environment ErrorstateREDstate REDstate Trap Table Uses of the Trap Categories Reset TrapsTrap Categories Deferred Traps Trap Type TT Trap ControlTrap-Table Entry Addresses PIL Control Sparc JPS1 Implementation-Dependent Traps Trap ProcessingException and Interrupt Descriptions Details of Supported TrapsPage Sparc V9 Memory Model on Memory Models Synchronizing Instruction and Data Memory Mode ControlOverview Sparc V9 Memory Model Release 1.0, 1 July Memory Models Page Table A-1Implementation-Specific Instructions Instruction Definitions SPARC64 V ExtensionsPage Block Load and Store Instructions VIS Invalid Valid Implementation-Dependent Instructions Call and Link Format Floating-Point Multiply-Add/SubtractPage Non-Trapping aexc When FSR.NS = Non-Trapping cexc When FSR.NS =Operation, and inexact, respectively Jump and Link Exceptions fpdisabled Format 3 Ldda Load Quadword, Atomic Physical Memory Barrier Bits in the cmask Field Order Constraints Imposed by mmask Bits Prefetch Data Partial Store VIS01816 Table A-7describes prefetch variants implemented in SPARC64 Read State RegisterTable A-7Prefetch Variants Deprecated Instructions Write State RegisterStore Barrier Page Ieee Std 754-1985 Requirements for Floating-Point Nonstandard ModeTraps Inhibiting Results Fpexceptionother Exception ftt=unfinishedFPop Generates an unfinishedFPop exception Denormalized number, eres is less than zeroUnfinishedFPop Boundary Conditions Table B-2unfinishedFPop Boundary Conditions Pessimistic Zero Table B-4Pessimistic Overflow Conditions Operation Under FSR.NS =Pessimistic Overflow Table B-3Conditions for a Pessimistic Zero UnfinishedFPop4 Floating-Point Exceptional Conditions and Results Yes and op2 Nv, dNaN Nonarithmetic Operations Under FSR.NS =Page Definition of an Implementation Dependency Implementation DependenciesPlease refer to Section C.1 of Commonality Please refer to Section C.2 of Commonality Hardware CharacteristicsImplementation Dependency Categories List of Implementation Dependencies Table C-1SPARC64 V Implementation Dependencies Deferred traps Reset trapEntering errorstate on implementation-dependent errors Errorstate processor state Floating-point underflow detection Data access FPU trapClean windows trap Flush instruction Unimplemented LDD trap SIRenable control flagMMU disabled prefetch behavior IMPDEPn instructions Implementation-dependent memory model Implicit ASI when TLUnimplemented values for PSTATE.MM Coherence and atomicity of memory operations Table C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 258 255256 257 Please refer to Appendix D of Commonality Formal Specification of the Memory ModelsPage Instruction65 Opcode MapsPage Virtual Address Translation Memory Management Unit Table F-1Organization of SPARC64 V TLBs Translation Table Entry TTE Release 1.0, 1 July Chapter F Memory Management Unit TSB Pointer Formation TSB OrganizationTSB Pointer Formation TLB miss 64 16-67 Faults and Traps Instructionaccessexception Reset, Disable, and REDstate Behavior Asimcntl Memory Control Register Accessing MMU RegistersAccess Modes Supervisor read/write Internal Registers and ASI operations JPS1TSBP 10.4 I/D TLB Data In, Data Access, and Tag Read RegistersTable F-3MCNTL Field Description RMDPage TLB# Table F-4MMU TLB Data Access Address Assignment Kbyte page entry MMU TLB Tag Access Register TSB Base Registers 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSRMMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR 10.7 I/D TSB Extension Registers EID Table F-5I-SFSRBit Description Table F-6describes the field encoding for ISFSR.FT FT60 Error DescriptionSFSRBit Description Table F-8D-SFSRBit Description 1 Isfsr Update Policy Table F-8D-SFSRBit Description 2 SFSRBit Description 3 Table F-9defines the encoding of the FT60 field Dsfsr Update Policy MMU Synchronous Fault Status Register FT Fault Type FieldFresh fault or miss3 Table F-11Bypass Attribute Bits on SPARC64 Table F-10DSFSR Update PolicyMMU Bypass Kbytes Automatic TLB Replacement Rule TLB Replacement PolicyRestriction of sTLB Entry Direct Replacement Page Please refer to Appendix G of Commonality Assembly Language SyntaxPage Please refer to Appendix H of Commonality Software ConsiderationsPage Please refer to Appendix I of Commonality Extending the Sparc V9 ArchitecturePage Please refer to Appendix K of Commonality Changes from Sparc V8 to SparcPage Please refer to Appendix J of Commonality Programming with the Memory ModelsPage SPARC64 V ASI Assignments Address Space IdentifiersSPARC64 V ASI Assignments 1 TBD SPARC64 V ASI Assignments 2 SPARC64 V ASI Assignments 3 Special Memory Access ASIs Partial Store ASIs Block Load and Store ASIs Interface Definition Barrier Assist for Parallel ProcessingHigh-Speed Lbsy Read Mechanism High-Speed BST Write Mechanism ASI RegistersLbsy Control Register ASICLBSYR0, ASICLBSYR1 Bstw Busy Status Register Asicbstwbusy Bstw Control Register ASICBSTW0, ASICBSTW1 Read Write is ignored Last Barrier Synchronization Status Read ASILBSYR0Barrier State Write ASIBSTW0, ASIBSTW1 EF16 Cache Types Cache Organization Level-1 Instruction Cache L1I Cache Table M-1L1I Cache Characteristics Level-2 Unified Cache L2 Cache Table M-2L1D Cache CharacteristicsTable M-3L2 Cache Characteristics Level-1 Data Cache L1D Cache Table M-5L2 Cache Moesi States Cache Coherency ProtocolsCache Control/Status Instructions Table M-4Relationships Between Cache Coherency Protocols ASIFLUSHL1I Flush Level-1 Instruction Cache Level-2 Cache Control Register ASIL2CTRL 3 L2 Diagnostics Tag ReadTable M-6ASIL2CTRL Register Bits ASIL2DIAGTAGREADREG 4 L2 Diagnostics Tag Read RegistersPage Interrupt Dispatch Interrupt Handling Membar Figure N-2is an example of the interrupt receive flow Interrupt Receive Interrupt Vector Dispatch Status Register Interrupt Global RegistersInterrupt-Related ASR Registers Interrupt Vector Dispatch Register Appendix contains these sections Reset, REDstate, and errorstateReset Types Power-on Reset POR Externally Initiated Reset XIR Watchdog Reset WDRSoftware-Initiated Reset SIR Figure O-1illustrates the processor state transition diagram REDstate and errorstate PA = 000007FFF000000016 Floating Point registers Processor State after Reset and in REDstateCPU Fatal Error state Integer registers Mask dependent TBA6315 ASI Register State After Reset and in REDstate 1 Table O-2ASR State after Reset and in REDstateCounter Others ASI Register State After Reset and in REDstate 2 ASI Register State After Reset and in REDstate 3 11011 Unchanged Operating Status Register Opsr Firmware Initialization Sequence Hardware Power-On Reset SequenceTo be defined later Page Error Classification Error HandlingFatal Error Urgent Error Errorstate Transition ErrorInstruction-Obstructing Error Urgent Error Independent of Instruction Execution Traps for Urgent Errors Restrainable ErrorCorrectable Error CE, corrected by hardware Table P-1Registers Related to Error Handling Action and Error ControlRegisters Related to Error Handling Following registers are related to the error handling Table P-2summarizes what happens when an error is detected Summary of Actions Upon Error DetectionTable P-2Action Upon Detection of an Error 1 Ideal specification Table P-2Action Upon Detection of an Error 2Deviation in SPARC64 Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Marking for Cacheable Data Error Table P-3Syndrome for Data Marked for Error Format of Error-Marking DataTable P-4Format of Error-Marked Data Table P-5ERRORMARKID Bit Description Table P-6shows the Errormarkid set by the CPU Table P-7Error Marking on SPARC64 IV and SPARC64 Difference Between Error Marking on SPARC64 IV Rteue Control of Error Action AsierrorcontrolValue in ASIERRORCONTROL, as defined in Table P-9 Table P-8 Asieidr Bit Description Ugehandler Weaked Always 0 Eeother Fatal Error and errorstate Transition ErrorTable P-10Format of Asistchgerrorinfo Bit Description 4C16 Types of errorstate Transition Errors Fatal Error TypesCurrent SPARC64 V implementation Ideal specification not implemented Urgent ErrorTable P-11ASIUGESR Bit Description 1 Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Instend Priv Mugedae Mugeiae Mugeiuge Action of asyncdataerror ADE TrapConditions that cause ADE trap Table P-11ASIUGESR Bit Description 4 State transition Set the specific register settingFollowing three sets of registers are updated Following actions are executed in this order Instend Update of ASIUGESR, as shown in Table P-13Instruction End-Method at ADE Trap Upon completion of a Retry or Done instruction Expected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap Data Access Errors Instruction Access ErrorsSee Appendix F, Memory Management Unit, for details Asiasyncfaultstatus Asiafsr Restrainable Errors Ceincomed DGL1$U2$STLB Implementation Deviation SPARC64 V sets UedstbetoUERAWL2$FILL UERAWL2$INSD WAY Contents Syndrome ASIASYNCFAULTADDRU2 register is described in Table P-17 Contents of PABIT423 Expected Software Handling of Restrainable ErrorsPage Terminology used in Table P-18is defined as follows Handling of Internal Register ErrorsRegister Error Handling Excluding ASRs and ASI Registers Table P-18shows error handling for most registers ADE trap, W ASR Error HandlingTable P-19shows the handling of ASR errors Table P-19ASR Error Handling Parity Always ASI Register Error HandlingError Protect Terminology used in Table P-20is defined as follows Error Detect Condition Correction Error Type Table P-20Handling of ASI Register Errors Table P-20shows the handling of ASI register errors Table P-20Handling of ASI Register Errors Error in D1 Cache Tag and I1 Cache Tag Cache Error HandlingHandling of a Cache Tag Error SPARC64 V Implementation and the Ideal Specification Error in U2 Unified Level 2 Cache Tag Handling of a D1 Cache Data Error Handling of an I1 Cache Data ErrorCorrectable Error in D1 Cache Data Marked Uncorrectable Error in D1 Cache Data Raw Uncorrectable Error in U2 Cache Data Handling of a U2 Cache Data ErrorCorrectable Error in U2 Cache Data Marked Uncorrectable Error in U2 Cache Data Way Reduction Condition Automatic Way Reduction of I1 Cache, D1 Cache, and U2 CacheI1 Cache Way Reduction U2 Cache Way Reduction D1 Cache Way Reduction Table P-22Error Protection and Detection of TLB Entries TLB Error HandlingHandling of TLB Entry Errors Error in TLB Entry Detected on Ldxa Instruction Access Automatic Way Reduction of sTLB STLB Way Reduction Handling of Extended UPA Bus Interface ErrorHandling of Extended UPA Address Bus Error Handling of Extended UPA Data Bus Error Correctable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Counter Clear/Set Performance InstrumentationPerformance Monitor Overview Sample Pseudocodes Counter Stop and Read Counter Event Selection and Start Table Q-1Events and Encoding of Performance Monitor Performance Monitor Description Events and Encoding of Performance Monitor Instruction Statistics Counts the committed Floating Multiply-and-Add instructions Instruction Count instructioncounts Trap-Related Statistics Counts the occurrences of data uTLB misses MMU Event CountersCounts the occurrences of Tcc instructions Counts the occurrences of instruction uTLB misses Counts the total latency of I1 cache misses Cache Event CountersCounts the occurrences of I1 cache misses Counts the occurrences of D1 cache misses Counts L2 cache references by demand read access Counts the occurrences of L2 cache miss by demand access Counts the number of Scpbreq packets received UPA Event CountersCounts the number of Sinvreq packets received Counts the number of Scpireq packets received Barrier-Assist ASI Read Count asirdbar Miscellaneous CountersPage Table R-1CPU’s UPA Port Slave Area Mapping UPA Programmer’s ModelMapping of the CPU’s UPA Port Slave Area Table R-1shows the mapping of the CPU’s UPA port slave area Table R-2UPA PortID Register Fields UPA PortID Register Upacap UPA Config RegisterTable R-3UPA Config Register Description UPA PortID Register Fields UPA Config Register Description Upccap PconUPCCAP2 MIDPage SPARC64 V and UltraSPARC-III Differences 1 Summary of Differences between SPARC64 V and UltraSPARC-III UPA Table T-1SPARC64 V and UltraSPARC-III Differences 2 Sfsr Table T-1SPARC64 V and UltraSPARC-III Differences 3Page General References BibliographyPlease refer to Bibliography in Commonality Page Auge IndexPage ASIINTRW133 Page DAE Error detection action155 DGL1$L2$STLB error194 DGL1$U2$STLB error195 Dmmu On Jmpl instruction error53 update during MMU trap90 Persistence38 ECCerror exception46, 153, 155 Statistics monitoring206-207 FSR FQ17 Immu Isfsr Update during MMU trap90 PSO41 RMO41 Lddfa instruction80 OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB Way reduction194 uDTLB10, 85 UITLB10, 85, 90 uncorrectable error152UnimplementedFPop floating-point trap type70