Fujitsu Fujitsu SPARC64 V manual Table C-1SPARC64 V Implementation Dependencies 8

TABLE C-1SPARC64 V Implementation Dependencies (8 of 11)

Nbr	SPARC64 V Implementation Notes	Page
218	async_data_error	39
	async_data_error trap is implemented in SPARC64 V, using tt = 4016. See
	Appendix P for details.
219	Asynchronous Fault Address Register (AFAR) allocation	177, 178
	SPARC64 V implements two AFARs:
	• VA = 0016 for an error occurring in D1 cache.
	• VA = 0816 for an error occurring in U2 cache.
220	Addition of logging and control registers for error handling	—
	SPARC64 V implements various features for sustaining reliability. See
	Appendix P for details.
221	Special/signalling ECCs	—
	The method to generate “special” or “signalling” ECCs and whether
	processor-ID is embedded into the data associated with special/signalling
	ECCs is implementation dependent.
222	TLB organization	85
	SPARC64 V has the following TLB organization:
	• Level-2 micro ITLB (uITLB), 32-way fully associative
	• Level-1 micro DTLB (uDTLB), 32-way fully associative
	• Level-2 IMMU-TLB—consisting of sITLB (set-associative Instruction TLB)
	and fITLB (fully associative Instruction TLB).
	• Level-2 DMMU-TLB—consisting of sDTLB (set-associative Data TLB) and
	fDTLB (fully associative Data TLB).
223	TLB multiple-hit detection	86
	On SPARC64 V, TLB multiple hit detection is supported. However, the
	multiple hit is not detected at every TLB reference. When the micro-TLB
	(uTLB), which is the cache of sTLB and fTLB, matches the virtual address,
	the multiple hit in sTLB and fTLB is not detected. The multiple hit is
	detected only when the micro-TLB mismatches and the main TLB is
	referenced.
224	MMU physical address width	86
	The SPARC64 V MMU implements 43-bit physical addresses. The PA field of
	the TTE holds a 43-bit physical address. Bits 46:43 of each TTE always read
	as 0 and writes to them are ignored. The MMU translates virtual addresses
	into 43-bit physical addresses. Each cache tag holds bits 42:6 of physical
	addresses.
225	TLB locking of entries	87
	In SPARC64 V, when a TTE with its lock bit set is written into TLB through
	the Data In register, the TTE is automatically written into the corresponding
	fully associative TLB and locked in the TLB. Otherwise, the TTE is written
	into the corresponding sTLB of fTLB, depending on its page size.
226	TTE support for CV bit	87
	SPARC64 V does not support the CV bit in TTE. Since I1 and D1 are
	virtually indexed caches, unaliasing is supported by SPARC64 V. See also
	impl. dep. #232.

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 77