Fujitsu Fujitsu SPARC64 V Table F-6describes the field encoding for ISFSR.FT, SFSRBit Description

TABLE F-5	I-SFSRBit Description
Bits	Field Name	RW	Description
Data <15>	TM	R/W	Translation miss. When TM = 1, it signifies an occurrence of a mITLB miss
			upon an instruction reference.
Data <13:7>	FT<6:0>	R/W	Fault type. Saves and indicates an exact condition that caused the recorded
			exception. See TABLE F-6 for the field encoding.
			In the IMMU, FT is valid only for an instruction_access_exception. The
			ISFSR.FT always reads as 0 for a fast_instruction_access_MMU_miss and
			reads 0116 for an instruction_access_exception, since no other fault types
			apply.
Data <5:4>	CT<1:0>	R/W	Context type; Saves the context attribute for the reference that invokes an
			exception. For nontranslating ASI or invalid ASI, ISFSR.CT = 1102.
			0002:	Primary
			0102:	Reserved
			1002:	Nucleus
			1102:	Reserved
Data <3>	PR	R/W	Privileged. Indicates the CPU privilege status during the instruction
			reference that generates the exception. This field is valid when
			ISFSR.FV = 1.
Data <1>	OW	R/W	Overwritten. Set when ISFSR.FV = 1 upon the detection of a exception.
			This means that the fault valid bit is not yet cleared when another fault is
			detected.
Data <0>	FV	R/W	Fault valid. Set when the IMMU detects an exception. The bit is not set on
			an IMMU miss. When the Fault Valid bit is not set, the values of the
			remaining fields in the ISFSR are undefined, except for an IMMU miss.

TABLE F-6describes the field encoding for ISFSR.FT.

TABLE F-6Instruction Synchronous Fault Status Register FT (Fault Type) Field

FT<6:0>	Error Description
0116	Privilege violation. Set when TTE.P = 1 and PSTATE.PRIV = 0 for the
	instruction reference.
0216	Reserved
0416	Reserved
0816	Reserved
1016	Reserved
2016	Reserved, since there is no virtual hole.
4016	Reserved, since there is no virtual hole.

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 99