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Fujitsu Fujitsu SPARC64 V manual Automatic Way Reduction of sTLB, Way Reduction Condition

Models: Fujitsu SPARC64 V

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When a parity error is detected in an ITLB entry when an LDXA instruction attempts to read ASI_ITLB_DATA_ACCESS or ASI_ITLB_TAG_ACCESS, hardware automatically demaps the entry and an instruction urgent error is indicated in ASI_UGESR.IUG_ITLB.

Error in sTLB Entry Detected During Virtual Address

Translation

When a parity error is detected in the sTLB entry during a virtual address translation, hardware automatically demaps the entry and does not report the error to software.

Error in fTLB Entry Detected During Virtual Address

Translation

When an fTLB tag has a parity error, the fTLB entry never matches any virtual address. An fTLB tag error in a locked entry causes a TLB miss for the virtual address already registered as the locked TLB entry.

A parity error in fTLB entry data is detected only when the tag of the fTLB entry matches a virtual address.

When a parity error in the fITLB is detected at the time of an instruction fetch, a precise instruction_access_error exception is generated. The parity error in the fITLB entry and the fITLB entry index is indicated in ASI_IFSR.

When a parity error in fDTLB is detected for the memory access of a load or store instruction, a precise data_access_error exception is generated. The parity error in the fDTLB entry and the fDTLB entry index is indicated in ASI_DFSR.

P.10.2 Automatic Way Reduction of sTLB

When frequent errors occur in sITLB and sDTLB, hardware automatically detects that condition and reduces the way, with no adverse effects on software.

Way Reduction Condition

Hardware counts TLB entry parity error occurrences for each sITLB way and sDTLB way. If the error count per unit of time exceeds a predefined threshold, hardware recognizes an sTLB way reduction condition.

196 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

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Fujitsu Fujitsu SPARC64 V manual Automatic Way Reduction of sTLB, Way Reduction Condition

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Traps InstructionsSparc JPS1 Implementation-Dependent Traps Memory ModelsImplementation Dependencies Level-1 Instruction Cache L1I Cache Cache Organization 125 Cache TypesReset, REDstate, and errorstate 137 Reset Types Error Handling 149 Error ClassificationFatal Error Asistchgerrorinfo UPA Programmer’s Model General ReferencesIndex Page Overview Navigating the SPARC64 V Implementation SupplementFonts and Notational Conventions High Reliability and High Integrity SPARC64 V processorMicroarchitecture for High Performance High IntegrationAdvanced RAS features for caches Advanced RAS features for the coreExtended RAS interface to software Component Overview Asynchronous data error ADE trap for additional errorsSX-Unit 2Execution Unit Major Blocks Instruction Control Unit IUExecution Unit EU 1Instruction Control Unit Major BlocksStorage Unit Major Blocks Storage Unit SU4Secondary Cache and External Access Unit Major Blocks Secondary Cache and External Access Unit SXUInstruction dispatch Synonym instruction initiation DefinitionsIssue-stalling Sync Synonym machine sync Page Architectural Overview Page Please refer to , Data Formats in Commonality Data FormatsPage Nonprivileged Registers RegistersFSRfloating-pointtraptype ftt Floating-Point State Register FSRFSRnonstandardfp NS FSRversion verFSR Conformance Privileged RegistersTick Tick Register Trap State Tstate Register1shows the values for the VER register for SPARC64 Version VER RegisterAncillary State Registers ASRs Performance Control Register PCR ASROvro OVFDispatch Control Register DCR ASR Accessibility as described above impl. dep. #250Registers Referenced Through ASIs Performance Instrumentation Counter PIC Register ASRVM70 PM70Instruction Trap Register Floating-Point Deferred-Trap Queue FQIU Deferred-Trap Queue Data Watchpoint RegistersInstructions Instruction ExecutionData Prefetch Instruction Prefetch 1SPARC64 V Syncing Instructions Syncing InstructionsInstruction Formats and Fields 2Instruction Fields Specific to SPARC64Yes Control transfer CTI Instruction CategoriesControl-Transfer Instructions CTIs Call and Jmpl InstructionsImplementation-Dependent Instructions Floating-Point Operate FPop InstructionsInstruction Fetch Stages Processor PipelineBrhis Execution Stages Issue StagesCompletion Stages Execution Stages for Cache AccessTraps Processor States, Normal and Special TrapsPlease refer to .1 of Commonality REDstate Execution Environment ErrorstateREDstate REDstate Trap TableUses of the Trap Categories Reset TrapsTrap Categories Deferred TrapsTrap Type TT Trap ControlTrap-Table Entry Addresses PIL ControlSparc JPS1 Implementation-Dependent Traps Trap ProcessingException and Interrupt Descriptions Details of Supported TrapsPage Sparc V9 Memory Model on Memory ModelsSynchronizing Instruction and Data Memory Mode ControlOverview Sparc V9 Memory ModelRelease 1.0, 1 July Memory Models Page Table A-1Implementation-Specific Instructions Instruction Definitions SPARC64 V ExtensionsPage Block Load and Store Instructions VIS Invalid Valid Implementation-Dependent Instructions Call and LinkFormat Floating-Point Multiply-Add/SubtractPage Non-Trapping cexc When FSR.NS = Non-Trapping aexc When FSR.NS =Operation, and inexact, respectively Jump and Link Exceptions fpdisabledFormat 3 Ldda Load Quadword, Atomic PhysicalMemory Barrier Bits in the cmask Field Order Constraints Imposed by mmask BitsPartial Store VIS Prefetch Data01816 Read State Register Table A-7describes prefetch variants implemented in SPARC64Table A-7Prefetch Variants Write State Register Deprecated InstructionsStore Barrier Page Floating-Point Nonstandard Mode Ieee Std 754-1985 Requirements forTraps Inhibiting Results Fpexceptionother Exception ftt=unfinishedFPop Denormalized number, eres is less than zero Generates an unfinishedFPop exceptionUnfinishedFPop Boundary Conditions Table B-2unfinishedFPop Boundary Conditions Pessimistic ZeroTable B-4Pessimistic Overflow Conditions Operation Under FSR.NS =Pessimistic Overflow Table B-3Conditions for a Pessimistic ZeroUnfinishedFPop4 Floating-Point Exceptional Conditions and ResultsYes and op2 Nv, dNaN Nonarithmetic Operations Under FSR.NS =Page Implementation Dependencies Definition of an Implementation DependencyPlease refer to Section C.1 of Commonality Please refer to Section C.2 of Commonality Hardware CharacteristicsImplementation Dependency Categories List of Implementation DependenciesTable C-1SPARC64 V Implementation Dependencies Deferred traps Reset trapEntering errorstate on implementation-dependent errors Errorstate processor stateFloating-point underflow detection Data access FPU trapClean windows trap Flush instructionUnimplemented LDD trap SIRenable control flagMMU disabled prefetch behavior IMPDEPn instructionsImplementation-dependent memory model Implicit ASI when TLUnimplemented values for PSTATE.MM Coherence and atomicity of memory operationsTable C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 258 255256 257Please refer to Appendix D of Commonality Formal Specification of the Memory ModelsPage Instruction65 Opcode MapsPage Virtual Address Translation Memory Management UnitTable F-1Organization of SPARC64 V TLBs Translation Table Entry TTERelease 1.0, 1 July Chapter F Memory Management Unit TSB Organization TSB Pointer FormationTSB Pointer Formation TLB miss 64 16-67 Faults and TrapsInstructionaccessexception Reset, Disable, and REDstate Behavior Asimcntl Memory Control Register Accessing MMU RegistersAccess Modes Supervisor read/write Internal Registers and ASI operationsJPS1TSBP 10.4 I/D TLB Data In, Data Access, and Tag Read RegistersTable F-3MCNTL Field Description RMDPage TLB# Table F-4MMU TLB Data Access Address AssignmentKbyte page entry MMU TLB Tag Access RegisterTSB Base Registers 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSRMMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR 10.7 I/D TSB Extension RegistersEID Table F-5I-SFSRBit DescriptionFT60 Error Description Table F-6describes the field encoding for ISFSR.FTSFSRBit Description Table F-8D-SFSRBit Description 1 Isfsr Update PolicyTable F-8D-SFSRBit Description 2 SFSRBit Description 3 Table F-9defines the encoding of the FT60 fieldMMU Synchronous Fault Status Register FT Fault Type Field Dsfsr Update PolicyFresh fault or miss3 Table F-11Bypass Attribute Bits on SPARC64 Table F-10DSFSR Update PolicyMMU Bypass KbytesTLB Replacement Policy Automatic TLB Replacement RuleRestriction of sTLB Entry Direct Replacement Page Please refer to Appendix G of Commonality Assembly Language SyntaxPage Please refer to Appendix H of Commonality Software ConsiderationsPage Please refer to Appendix I of Commonality Extending the Sparc V9 ArchitecturePage Please refer to Appendix K of Commonality Changes from Sparc V8 to SparcPage Please refer to Appendix J of Commonality Programming with the Memory ModelsPage Address Space Identifiers SPARC64 V ASI AssignmentsSPARC64 V ASI Assignments 1 TBD SPARC64 V ASI Assignments 2SPARC64 V ASI Assignments 3 Special Memory Access ASIsPartial Store ASIs Block Load and Store ASIsBarrier Assist for Parallel Processing Interface DefinitionHigh-Speed Lbsy Read Mechanism ASI Registers High-Speed BST Write MechanismLbsy Control Register ASICLBSYR0, ASICLBSYR1 Bstw Busy Status Register Asicbstwbusy Bstw Control Register ASICBSTW0, ASICBSTW1Read Write is ignored Last Barrier Synchronization Status Read ASILBSYR0Barrier State Write ASIBSTW0, ASIBSTW1 EF16Cache Types Cache OrganizationLevel-1 Instruction Cache L1I Cache Table M-1L1I Cache CharacteristicsLevel-2 Unified Cache L2 Cache Table M-2L1D Cache CharacteristicsTable M-3L2 Cache Characteristics Level-1 Data Cache L1D CacheTable M-5L2 Cache Moesi States Cache Coherency ProtocolsCache Control/Status Instructions Table M-4Relationships Between Cache Coherency ProtocolsASIFLUSHL1I Flush Level-1 Instruction Cache3 L2 Diagnostics Tag Read Level-2 Cache Control Register ASIL2CTRLTable M-6ASIL2CTRL Register Bits ASIL2DIAGTAGREADREG 4 L2 Diagnostics Tag Read RegistersPage Interrupt Dispatch Interrupt HandlingMembar Figure N-2is an example of the interrupt receive flow Interrupt ReceiveInterrupt Vector Dispatch Status Register Interrupt Global RegistersInterrupt-Related ASR Registers Interrupt Vector Dispatch RegisterAppendix contains these sections Reset, REDstate, and errorstateReset Types Power-on Reset PORWatchdog Reset WDR Externally Initiated Reset XIRSoftware-Initiated Reset SIR Figure O-1illustrates the processor state transition diagram REDstate and errorstatePA = 000007FFF000000016 Floating Point registers Processor State after Reset and in REDstateCPU Fatal Error state Integer registersMask dependent TBA6315Table O-2ASR State after Reset and in REDstate ASI Register State After Reset and in REDstate 1Counter Others ASI Register State After Reset and in REDstate 2ASI Register State After Reset and in REDstate 3 11011 Unchanged Operating Status Register OpsrHardware Power-On Reset Sequence Firmware Initialization SequenceTo be defined later Page Error Handling Error ClassificationFatal Error Errorstate Transition Error Urgent ErrorInstruction-Obstructing Error Urgent Error Independent of Instruction Execution Restrainable Error Traps for Urgent ErrorsCorrectable Error CE, corrected by hardware Table P-1Registers Related to Error Handling Action and Error ControlRegisters Related to Error Handling Following registers are related to the error handlingSummary of Actions Upon Error Detection Table P-2summarizes what happens when an error is detectedTable P-2Action Upon Detection of an Error 1 Table P-2Action Upon Detection of an Error 2 Ideal specificationDeviation in SPARC64 Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Marking for Cacheable Data ErrorFormat of Error-Marking Data Table P-3Syndrome for Data Marked for ErrorTable P-4Format of Error-Marked Data Table P-5ERRORMARKID Bit Description Table P-6shows the Errormarkid set by the CPUTable P-7Error Marking on SPARC64 IV and SPARC64 Difference Between Error Marking on SPARC64 IVRteue Control of Error Action AsierrorcontrolValue in ASIERRORCONTROL, as defined in Table P-9 Table P-8 Asieidr Bit DescriptionUgehandler WeakedAlways 0 Eeother Fatal Error and errorstate Transition ErrorTable P-10Format of Asistchgerrorinfo Bit Description 4C16Fatal Error Types Types of errorstate Transition ErrorsCurrent SPARC64 V implementation Urgent Error Ideal specification not implementedTable P-11ASIUGESR Bit Description 1 Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Instend Priv Mugedae Mugeiae Mugeiuge Action of asyncdataerror ADE TrapConditions that cause ADE trap Table P-11ASIUGESR Bit Description 4State transition Set the specific register settingFollowing three sets of registers are updated Following actions are executed in this orderInstend Update of ASIUGESR, as shown in Table P-13Instruction End-Method at ADE Trap Upon completion of a Retry or Done instructionExpected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap Instruction Access Errors Data Access ErrorsSee Appendix F, Memory Management Unit, for details Asiasyncfaultstatus Asiafsr Restrainable ErrorsCeincomed DGL1$U2$STLBImplementation Deviation SPARC64 V sets UedstbetoUERAWL2$FILL UERAWL2$INSDWAY ContentsSyndrome ASIASYNCFAULTADDRU2 register is described in Table P-17Contents of PABIT423 Expected Software Handling of Restrainable ErrorsPage Terminology used in Table P-18is defined as follows Handling of Internal Register ErrorsRegister Error Handling Excluding ASRs and ASI Registers Table P-18shows error handling for most registersADE trap, W ASR Error HandlingTable P-19shows the handling of ASR errors Table P-19ASR Error HandlingParity Always ASI Register Error HandlingError Protect Terminology used in Table P-20is defined as followsError Detect Condition Correction Error TypeTable P-20Handling of ASI Register Errors Table P-20shows the handling of ASI register errorsTable P-20Handling of ASI Register Errors Error in D1 Cache Tag and I1 Cache Tag Cache Error HandlingHandling of a Cache Tag Error SPARC64 V Implementation and the Ideal SpecificationError in U2 Unified Level 2 Cache Tag Handling of an I1 Cache Data Error Handling of a D1 Cache Data ErrorCorrectable Error in D1 Cache Data Marked Uncorrectable Error in D1 Cache Data Raw Uncorrectable Error in U2 Cache Data Handling of a U2 Cache Data ErrorCorrectable Error in U2 Cache Data Marked Uncorrectable Error in U2 Cache DataAutomatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache Way Reduction ConditionI1 Cache Way Reduction U2 Cache Way Reduction D1 Cache Way ReductionTable P-22Error Protection and Detection of TLB Entries TLB Error HandlingHandling of TLB Entry Errors Error in TLB Entry Detected on Ldxa Instruction AccessAutomatic Way Reduction of sTLB STLB Way Reduction Handling of Extended UPA Bus Interface ErrorHandling of Extended UPA Address Bus Error Handling of Extended UPA Data Bus ErrorCorrectable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Counter Clear/Set Performance InstrumentationPerformance Monitor Overview Sample PseudocodesCounter Stop and Read Counter Event Selection and StartTable Q-1Events and Encoding of Performance Monitor Performance Monitor DescriptionEvents and Encoding of Performance Monitor Instruction StatisticsCounts the committed Floating Multiply-and-Add instructions Instruction Count instructioncountsTrap-Related Statistics Counts the occurrences of data uTLB misses MMU Event CountersCounts the occurrences of Tcc instructions Counts the occurrences of instruction uTLB missesCounts the total latency of I1 cache misses Cache Event CountersCounts the occurrences of I1 cache misses Counts the occurrences of D1 cache missesCounts L2 cache references by demand read access Counts the occurrences of L2 cache miss by demand accessCounts the number of Scpbreq packets received UPA Event CountersCounts the number of Sinvreq packets received Counts the number of Scpireq packets receivedBarrier-Assist ASI Read Count asirdbar Miscellaneous CountersPage Table R-1CPU’s UPA Port Slave Area Mapping UPA Programmer’s ModelMapping of the CPU’s UPA Port Slave Area Table R-1shows the mapping of the CPU’s UPA port slave areaTable R-2UPA PortID Register Fields UPA PortID RegisterUpacap UPA Config RegisterTable R-3UPA Config Register Description UPA PortID Register FieldsUPA Config Register Description Upccap PconUPCCAP2 MIDPage SPARC64 V and UltraSPARC-III Differences 1 Summary of Differences between SPARC64 V and UltraSPARC-IIIUPA Table T-1SPARC64 V and UltraSPARC-III Differences 2Sfsr Table T-1SPARC64 V and UltraSPARC-III Differences 3Page Bibliography General ReferencesPlease refer to Bibliography in Commonality Page Auge IndexPage ASIINTRW133 Page DAE Error detection action155DGL1$L2$STLB error194 DGL1$U2$STLB error195 Dmmu On Jmpl instruction error53 update during MMU trap90Persistence38 ECCerror exception46, 153, 155Statistics monitoring206-207 FSR FQ17Immu Isfsr Update during MMU trap90PSO41 RMO41 Lddfa instruction80OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB UITLB10, 85, 90 uncorrectable error152 Way reduction194 uDTLB10, 85UnimplementedFPop floating-point trap type70