Fujitsu Fujitsu SPARC64 V manual TLB Error Handling, Handling of TLB Entry Errors

ASI_UGESR.IUG_DTLB

2.Otherwise:

■All entries in available U2 cache ways, including way W, are invalidated to retain system consistency.

■Way W becomes unavailable and is never refilled.

■The restrainable error ASI_AFSR.DG_L1$U2$STLB is reported to software.

P.10 TLB Error Handling

This section describes how TLB entry errors and sTLB way reduction are handled.

P.10.1 Handling of TLB Entry Errors

Error protection and error detection in TLB entries are described in

TABLE P-22.

TABLE P-22Error Protection and Detection of TLB Entries

TLB type	Field	Error Protection	Detectable Error
sITLB and sDTLB	tag	Parity	Parity error (Uncorrectable)
sITLB and sDTLB	data	Parity	Parity error (Uncorrectable)
fITLB and fDTLB	lock bit	Triplicated	None; the value is determined by majority
fITLB and fDTLB	tag except lock bit	Parity	Parity error (Uncorrectable)
fITLB and fDTLB	data	Parity	Parity error

Errors can occur during the following events:

■Access by LDXA instruction

■Virtual address translation (sTLB)

■Virtual address translation (fTLB)

Error in TLB Entry Detected on LDXA Instruction Access

If a parity error is detected in a DTLB entry when an LDXA instruction attempts to read ASI_DTLB_DATA_ACCESS or ASI_DTLB_TAG_ACCESS, hardware automatically demaps the entry and an instruction urgent error is indicated in

.

Release 1.0, 1 July 2002 F. Chapter P Error Handling 195