Release 1.0, 1 July Memory Models | Fujitsu Fujitsu SPARC64 V

corresponding locations in all instruction caches; references to any instruction cache cause corresponding modified data to be flushed and corresponding unmodified data to be invalidated from all data caches. The flush operation is still operative in SPARC64 V, however.

Since the FLUSH instruction synchronizes the processor, the total latency varies depending on the situation in SPARC64 V. Assuming all prior instructions are completed, the latency of FLUSH is 18 CPU cycles.

Release 1.0, 1 July 2002

F. Chapter 8 Memory Models 43

Image 54

Fujitsu Fujitsu SPARC64 V manual Release 1.0, 1 July Memory Models

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Instructions Traps Sparc JPS1 Implementation-Dependent Traps Memory ModelsImplementation Dependencies Cache Organization 125 Cache Types Level-1 Instruction Cache L1I Cache Reset, REDstate, and errorstate 137 Reset Types Error Handling 149 Error ClassificationFatal Error Asistchgerrorinfo UPA Programmer’s Model General ReferencesIndex Page Overview Navigating the SPARC64 V Implementation SupplementFonts and Notational Conventions High Integration SPARC64 V processorMicroarchitecture for High Performance High Reliability and High Integrity Advanced RAS features for caches Advanced RAS features for the coreExtended RAS interface to software Asynchronous data error ADE trap for additional errors Component Overview SX-Unit 1Instruction Control Unit Major Blocks Instruction Control Unit IUExecution Unit EU 2Execution Unit Major Blocks Storage Unit SU Storage Unit Major Blocks Secondary Cache and External Access Unit SXU 4Secondary Cache and External Access Unit Major Blocks Definitions Instruction dispatch Synonym instruction initiation Issue-stalling Sync Synonym machine sync Page Architectural Overview Page Data Formats Please refer to , Data Formats in CommonalityPage Registers Nonprivileged Registers FSRversion ver Floating-Point State Register FSRFSRnonstandardfp NS FSRfloating-pointtraptype ftt Trap State Tstate Register Privileged RegistersTick Tick Register FSR Conformance Performance Control Register PCR ASR Version VER RegisterAncillary State Registers ASRs 1shows the values for the VER register for SPARC64 OVF Ovro Performance Instrumentation Counter PIC Register ASR Accessibility as described above impl. dep. #250Registers Referenced Through ASIs Dispatch Control Register DCR ASR PM70 VM70 Data Watchpoint Registers Floating-Point Deferred-Trap Queue FQIU Deferred-Trap Queue Instruction Trap Register Instructions Instruction ExecutionData Prefetch Instruction Prefetch Syncing Instructions 1SPARC64 V Syncing Instructions Instruction Formats and Fields 2Instruction Fields Specific to SPARC64Yes Call and Jmpl Instructions Instruction CategoriesControl-Transfer Instructions CTIs Control transfer CTI Floating-Point Operate FPop Instructions Implementation-Dependent Instructions Processor Pipeline Instruction Fetch Stages Brhis Issue Stages Execution Stages Execution Stages for Cache Access Completion Stages Traps Processor States, Normal and Special TrapsPlease refer to .1 of Commonality REDstate Trap Table ErrorstateREDstate REDstate Execution Environment Deferred Traps Reset TrapsTrap Categories Uses of the Trap Categories PIL Control Trap ControlTrap-Table Entry Addresses Trap Type TT Details of Supported Traps Trap ProcessingException and Interrupt Descriptions Sparc JPS1 Implementation-Dependent TrapsPage Memory Models Sparc V9 Memory Model on Sparc V9 Memory Model Mode ControlOverview Synchronizing Instruction and Data Memory Release 1.0, 1 July Memory Models Page Instruction Definitions SPARC64 V Extensions Table A-1Implementation-Specific InstructionsPage Block Load and Store Instructions VIS Invalid Valid Call and Link Implementation-Dependent Instructions Floating-Point Multiply-Add/Subtract FormatPage Non-Trapping cexc When FSR.NS = Non-Trapping aexc When FSR.NS =Operation, and inexact, respectively Exceptions fpdisabled Jump and Link Load Quadword, Atomic Physical Format 3 Ldda Memory Barrier Order Constraints Imposed by mmask Bits Bits in the cmask Field Partial Store VIS Prefetch Data01816 Read State Register Table A-7describes prefetch variants implemented in SPARC64Table A-7Prefetch Variants Write State Register Deprecated InstructionsStore Barrier Page Floating-Point Nonstandard Mode Ieee Std 754-1985 Requirements forTraps Inhibiting Results Fpexceptionother Exception ftt=unfinishedFPop Denormalized number, eres is less than zero Generates an unfinishedFPop exceptionUnfinishedFPop Boundary Conditions Pessimistic Zero Table B-2unfinishedFPop Boundary Conditions Table B-3Conditions for a Pessimistic Zero Operation Under FSR.NS =Pessimistic Overflow Table B-4Pessimistic Overflow Conditions Floating-Point Exceptional Conditions and Results UnfinishedFPop4 Nonarithmetic Operations Under FSR.NS = Yes and op2 Nv, dNaNPage Implementation Dependencies Definition of an Implementation DependencyPlease refer to Section C.1 of Commonality List of Implementation Dependencies Hardware CharacteristicsImplementation Dependency Categories Please refer to Section C.2 of Commonality Table C-1SPARC64 V Implementation Dependencies Errorstate processor state Reset trapEntering errorstate on implementation-dependent errors Deferred traps Flush instruction Data access FPU trapClean windows trap Floating-point underflow detection IMPDEPn instructions SIRenable control flagMMU disabled prefetch behavior Unimplemented LDD trap Coherence and atomicity of memory operations Implicit ASI when TLUnimplemented values for PSTATE.MM Implementation-dependent memory model Table C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 257 255256 258 Formal Specification of the Memory Models Please refer to Appendix D of CommonalityPage Opcode Maps Instruction65Page Memory Management Unit Virtual Address Translation Translation Table Entry TTE Table F-1Organization of SPARC64 V TLBs Release 1.0, 1 July Chapter F Memory Management Unit TSB Organization TSB Pointer FormationTSB Pointer Formation Faults and Traps TLB miss 64 16-67 Instructionaccessexception Reset, Disable, and REDstate Behavior Internal Registers and ASI operations Accessing MMU RegistersAccess Modes Supervisor read/write Asimcntl Memory Control Register RMD 10.4 I/D TLB Data In, Data Access, and Tag Read RegistersTable F-3MCNTL Field Description JPS1TSBPPage Table F-4MMU TLB Data Access Address Assignment TLB# MMU TLB Tag Access Register Kbyte page entry 10.7 I/D TSB Extension Registers 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSRMMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR TSB Base Registers Table F-5I-SFSRBit Description EID FT60 Error Description Table F-6describes the field encoding for ISFSR.FTSFSRBit Description Isfsr Update Policy Table F-8D-SFSRBit Description 1 Table F-8D-SFSRBit Description 2 Table F-9defines the encoding of the FT60 field SFSRBit Description 3 MMU Synchronous Fault Status Register FT Fault Type Field Dsfsr Update PolicyFresh fault or miss3 Kbytes Table F-10DSFSR Update PolicyMMU Bypass Table F-11Bypass Attribute Bits on SPARC64 TLB Replacement Policy Automatic TLB Replacement RuleRestriction of sTLB Entry Direct Replacement Page Assembly Language Syntax Please refer to Appendix G of CommonalityPage Software Considerations Please refer to Appendix H of CommonalityPage Extending the Sparc V9 Architecture Please refer to Appendix I of CommonalityPage Changes from Sparc V8 to Sparc Please refer to Appendix K of CommonalityPage Programming with the Memory Models Please refer to Appendix J of CommonalityPage Address Space Identifiers SPARC64 V ASI AssignmentsSPARC64 V ASI Assignments 1 SPARC64 V ASI Assignments 2 TBD Special Memory Access ASIs SPARC64 V ASI Assignments 3 Block Load and Store ASIs Partial Store ASIs Barrier Assist for Parallel Processing Interface DefinitionHigh-Speed Lbsy Read Mechanism ASI Registers High-Speed BST Write MechanismLbsy Control Register ASICLBSYR0, ASICLBSYR1 Bstw Control Register ASICBSTW0, ASICBSTW1 Bstw Busy Status Register Asicbstwbusy EF16 Last Barrier Synchronization Status Read ASILBSYR0Barrier State Write ASIBSTW0, ASIBSTW1 Read Write is ignored Cache Organization Cache Types Table M-1L1I Cache Characteristics Level-1 Instruction Cache L1I Cache Level-1 Data Cache L1D Cache Table M-2L1D Cache CharacteristicsTable M-3L2 Cache Characteristics Level-2 Unified Cache L2 Cache Table M-4Relationships Between Cache Coherency Protocols Cache Coherency ProtocolsCache Control/Status Instructions Table M-5L2 Cache Moesi States Flush Level-1 Instruction Cache ASIFLUSHL1I 3 L2 Diagnostics Tag Read Level-2 Cache Control Register ASIL2CTRLTable M-6ASIL2CTRL Register Bits 4 L2 Diagnostics Tag Read Registers ASIL2DIAGTAGREADREGPage Interrupt Handling Interrupt Dispatch Membar Interrupt Receive Figure N-2is an example of the interrupt receive flow Interrupt Vector Dispatch Register Interrupt Global RegistersInterrupt-Related ASR Registers Interrupt Vector Dispatch Status Register Power-on Reset POR Reset, REDstate, and errorstateReset Types Appendix contains these sections Watchdog Reset WDR Externally Initiated Reset XIRSoftware-Initiated Reset SIR REDstate and errorstate Figure O-1illustrates the processor state transition diagram PA = 000007FFF000000016 Integer registers Processor State after Reset and in REDstateCPU Fatal Error state Floating Point registers TBA6315 Mask dependent Table O-2ASR State after Reset and in REDstate ASI Register State After Reset and in REDstate 1Counter ASI Register State After Reset and in REDstate 2 Others ASI Register State After Reset and in REDstate 3 Operating Status Register Opsr 11011 Unchanged Hardware Power-On Reset Sequence Firmware Initialization SequenceTo be defined later Page Error Handling Error ClassificationFatal Error Errorstate Transition Error Urgent ErrorInstruction-Obstructing Error Urgent Error Independent of Instruction Execution Restrainable Error Traps for Urgent ErrorsCorrectable Error CE, corrected by hardware Following registers are related to the error handling Action and Error ControlRegisters Related to Error Handling Table P-1Registers Related to Error Handling Summary of Actions Upon Error Detection Table P-2summarizes what happens when an error is detectedTable P-2Action Upon Detection of an Error 1 Table P-2Action Upon Detection of an Error 2 Ideal specificationDeviation in SPARC64 Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Error Marking for Cacheable Data Format of Error-Marking Data Table P-3Syndrome for Data Marked for ErrorTable P-4Format of Error-Marked Data Table P-6shows the Errormarkid set by the CPU Table P-5ERRORMARKID Bit Description Difference Between Error Marking on SPARC64 IV Table P-7Error Marking on SPARC64 IV and SPARC64 Table P-8 Asieidr Bit Description Control of Error Action AsierrorcontrolValue in ASIERRORCONTROL, as defined in Table P-9 Rteue Weaked Ugehandler 4C16 Fatal Error and errorstate Transition ErrorTable P-10Format of Asistchgerrorinfo Bit Description Always 0 Eeother Fatal Error Types Types of errorstate Transition ErrorsCurrent SPARC64 V implementation Urgent Error Ideal specification not implementedTable P-11ASIUGESR Bit Description 1 Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Table P-11ASIUGESR Bit Description 4 Action of asyncdataerror ADE TrapConditions that cause ADE trap Instend Priv Mugedae Mugeiae Mugeiuge Following actions are executed in this order Set the specific register settingFollowing three sets of registers are updated State transition Upon completion of a Retry or Done instruction Update of ASIUGESR, as shown in Table P-13Instruction End-Method at ADE Trap Instend Expected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap Instruction Access Errors Data Access ErrorsSee Appendix F, Memory Management Unit, for details Restrainable Errors Asiasyncfaultstatus Asiafsr DGL1$U2$STLB Ceincomed UERAWL2$INSD UedstbetoUERAWL2$FILL Implementation Deviation SPARC64 V sets Contents WAY ASIASYNCFAULTADDRU2 register is described in Table P-17 Syndrome Expected Software Handling of Restrainable Errors Contents of PABIT423Page Table P-18shows error handling for most registers Handling of Internal Register ErrorsRegister Error Handling Excluding ASRs and ASI Registers Terminology used in Table P-18is defined as follows Table P-19ASR Error Handling ASR Error HandlingTable P-19shows the handling of ASR errors ADE trap, W Terminology used in Table P-20is defined as follows ASI Register Error HandlingError Protect Parity Always Error Detect Condition Error Type Correction Table P-20shows the handling of ASI register errors Table P-20Handling of ASI Register Errors Table P-20Handling of ASI Register Errors SPARC64 V Implementation and the Ideal Specification Cache Error HandlingHandling of a Cache Tag Error Error in D1 Cache Tag and I1 Cache Tag Error in U2 Unified Level 2 Cache Tag Handling of an I1 Cache Data Error Handling of a D1 Cache Data ErrorCorrectable Error in D1 Cache Data Marked Uncorrectable Error in D1 Cache Data Marked Uncorrectable Error in U2 Cache Data Handling of a U2 Cache Data ErrorCorrectable Error in U2 Cache Data Raw Uncorrectable Error in U2 Cache Data Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache Way Reduction ConditionI1 Cache Way Reduction D1 Cache Way Reduction U2 Cache Way Reduction Error in TLB Entry Detected on Ldxa Instruction Access TLB Error HandlingHandling of TLB Entry Errors Table P-22Error Protection and Detection of TLB Entries Automatic Way Reduction of sTLB Handling of Extended UPA Data Bus Error Handling of Extended UPA Bus Interface ErrorHandling of Extended UPA Address Bus Error STLB Way Reduction Correctable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Sample Pseudocodes Performance InstrumentationPerformance Monitor Overview Counter Clear/Set Counter Event Selection and Start Counter Stop and Read Performance Monitor Description Table Q-1Events and Encoding of Performance Monitor Instruction Statistics Events and Encoding of Performance Monitor Instruction Count instructioncounts Counts the committed Floating Multiply-and-Add instructions Trap-Related Statistics Counts the occurrences of instruction uTLB misses MMU Event CountersCounts the occurrences of Tcc instructions Counts the occurrences of data uTLB misses Counts the occurrences of D1 cache misses Cache Event CountersCounts the occurrences of I1 cache misses Counts the total latency of I1 cache misses Counts the occurrences of L2 cache miss by demand access Counts L2 cache references by demand read access Counts the number of Scpireq packets received UPA Event CountersCounts the number of Sinvreq packets received Counts the number of Scpbreq packets received Miscellaneous Counters Barrier-Assist ASI Read Count asirdbarPage Table R-1shows the mapping of the CPU’s UPA port slave area UPA Programmer’s ModelMapping of the CPU’s UPA Port Slave Area Table R-1CPU’s UPA Port Slave Area Mapping UPA PortID Register Table R-2UPA PortID Register Fields UPA PortID Register Fields UPA Config RegisterTable R-3UPA Config Register Description Upacap UPA Config Register Description MID PconUPCCAP2 UpccapPage Summary of Differences between SPARC64 V and UltraSPARC-III SPARC64 V and UltraSPARC-III Differences 1 Table T-1SPARC64 V and UltraSPARC-III Differences 2 UPA Table T-1SPARC64 V and UltraSPARC-III Differences 3 SfsrPage Bibliography General ReferencesPlease refer to Bibliography in Commonality Page Index AugePage ASIINTRW133 Page Error detection action155 DAE DGL1$L2$STLB error194 DGL1$U2$STLB error195 On Jmpl instruction error53 update during MMU trap90 Dmmu ECCerror exception46, 153, 155 Persistence38 Statistics monitoring206-207 FQ17 FSR Immu Update during MMU trap90 Isfsr Lddfa instruction80 PSO41 RMO41 OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB UITLB10, 85, 90 uncorrectable error152 Way reduction194 uDTLB10, 85UnimplementedFPop floating-point trap type70