TABLE C-1SPARC64 V Implementation Dependencies

(3 of 11)

 

 

 

Nbr

SPARC64 V Implementation Notes

Page

 

 

 

32

Deferred traps

37, 149

 

SPARC64 V signals a deferred trap in a few of its severe error conditions.

 

SPARC64 V does not contain a deferred trap queue.

33

Trap precision

37

 

There are no deferred traps in SPARC64 V other than the trap caused by a

 

few severe error conditions. All traps that occur as the result of program

 

execution are precise.

 

34

Interrupt clearing

For details of interrupt handling see Appendix N, Interrupt Handling.

35 Implementation-dependent traps39, 39

SPARC64 V supports the following traps that are implementation dependent:

interrupt_vector_trap (tt = 06016)

PA_watchpoint (tt = 06116)

VA_watchpoint (tt = 06216)

ECC_error (tt = 06316)

fast_instruction_access_MMU_miss (tt = 06416 through 06716)

fast_data_access_MMU_miss (tt = 06816 through 06B16)

fast_data_access_protection (tt = 06C16 through 06F16)

async_data_error (tt = 04016)

36

Trap priorities

38

 

SPARC64 V’s implementation-dependent traps have the following

 

 

priorities:

 

 

interrupt_vector_trap (priority=16)

 

 

PA_watchpoint (priority=12)

 

 

VA_watchpoint (priority=1)

 

 

ECC_error (priority=33)

 

 

fast_instruction_access_MMU_miss (priority = 2)

 

 

fast_data_access_MMU_miss (priority = 12)

 

 

fast_data_access_protection (priority = 12)

 

 

async_data_error (priority = 2)

 

37

Reset trap

37

 

SPARC64 V implements power-on reset (POR) and watchdog reset.

 

38

Effect of reset trap on implementation-dependent registers

141

 

See Section O.3, Processor State after Reset and in RED_state, on page 141.

 

39

Entering error_state on implementation-dependent errors

36

 

CPU watchdog timeout at 233 ticks, a normal trap, or an SIR at TL = MAXTL

 

 

causes the CPU to enter error_state.

 

40

Error_state processor state

36

 

SPARC64 V optionally takes a watchdog reset trap after entry to

 

 

error_state. Most error-logging register state will be preserved. (See also

 

 

impl. dep. #254.)

 

41Reserved.

72 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

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Fujitsu Fujitsu SPARC64 V Deferred traps, Trap precision, Interrupt clearing, Implementation-dependent traps39, Reset trap