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Fujitsu Fujitsu SPARC64 V Expected Software Handling of Restrainable Errors, Contents of PABIT423

Models: Fujitsu SPARC64 V

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TABLE P-17ASI_ASYNC_FAULT_ADDR_U2 (ASI_AFAR_U2) Register Bit Description (Continued)

Bit	Name	R/W	Description

42:3	PA_BIT42_3	R		Physical address bit 42:3. Contains the value indicated by
				ASI_AFAR_U2.CONTENTS, as shown below:

				ASI_AFAR_U2.CONTENTS Error Name		Contents of PA_BIT42_3

				4016	CE_INCOMED	The physical address of the
						doubleword with the error.
			8016		UE_RAW_L2$FILL	The physical address of the
						doubleword with the error.
				C016	UE_RAW_L2$INSD	The physical address of the
						cache line (64-byte block) with
						the error. The least significant 3
						bits in the PA_BIT42_3 field
						are invalid and unpredictable.

Others	Reserved	R		Always read as 0.
All		W		Any write access sets all fields in this register to 0. That is, when a program
				writes to ASI_AFAR_U2, the entire ASI_AFAR_U2 is set to 0 regardless of the
				write value; any error recorded in ASI_AFAR_U2 is expunged.

P.7.4 Expected Software Handling of Restrainable Errors

Error recording and information is expected for all restrainable errors.

The expected software recovery from each type of each restrainable error is described below.

■ASI_AFSR.DG_L1$U2$STLB — The following status for the CPU is reported:

■Performance is degraded by the way reduction in I1$, D1$, U2$, sITLB, or sDTLB.

■CPU availability may be slightly down. If only one way facility is available among I1$, D1$, U2$, sITLB, and sDTLB and further way reduction is detected for this facility, the error_state transition error is detected.

Software stops the use of the CPU, if required.

■ASI_AFSR.CE_INCOMED — If ASI_AFAR_U2 contains CE_INCOMED information and the physical address of the error indicates the cacheable area, the following software sequence to correct the memory block is expected:

a. Make the U2 cache line with the CE detection dirty without changing the data. Use the CASA instruction to write that same data to the U2 cache line.

Release 1.0, 1 July 2002

F. Chapter P Error Handling 179

Image 190

Fujitsu Fujitsu SPARC64 V manual Expected Software Handling of Restrainable Errors, Contents of PABIT423

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Instructions TrapsMemory Models Sparc JPS1 Implementation-Dependent TrapsImplementation Dependencies Cache Organization 125 Cache Types Level-1 Instruction Cache L1I CacheError Handling 149 Error Classification Reset, REDstate, and errorstate 137 Reset TypesFatal Error Asistchgerrorinfo General References UPA Programmer’s ModelIndex Page Navigating the SPARC64 V Implementation Supplement OverviewFonts and Notational Conventions High Integration SPARC64 V processorMicroarchitecture for High Performance High Reliability and High IntegrityAdvanced RAS features for the core Advanced RAS features for cachesExtended RAS interface to software Asynchronous data error ADE trap for additional errors Component OverviewSX-Unit 1Instruction Control Unit Major Blocks Instruction Control Unit IUExecution Unit EU 2Execution Unit Major BlocksStorage Unit SU Storage Unit Major BlocksSecondary Cache and External Access Unit SXU 4Secondary Cache and External Access Unit Major BlocksDefinitions Instruction dispatch Synonym instruction initiationIssue-stalling Sync Synonym machine sync Page Architectural Overview Page Data Formats Please refer to , Data Formats in CommonalityPage Registers Nonprivileged RegistersFSRversion ver Floating-Point State Register FSRFSRnonstandardfp NS FSRfloating-pointtraptype fttTrap State Tstate Register Privileged RegistersTick Tick Register FSR ConformancePerformance Control Register PCR ASR Version VER RegisterAncillary State Registers ASRs 1shows the values for the VER register for SPARC64OVF OvroPerformance Instrumentation Counter PIC Register ASR Accessibility as described above impl. dep. #250Registers Referenced Through ASIs Dispatch Control Register DCR ASRPM70 VM70Data Watchpoint Registers Floating-Point Deferred-Trap Queue FQIU Deferred-Trap Queue Instruction Trap RegisterInstruction Execution InstructionsData Prefetch Instruction Prefetch Syncing Instructions 1SPARC64 V Syncing Instructions2Instruction Fields Specific to SPARC64 Instruction Formats and FieldsYes Call and Jmpl Instructions Instruction CategoriesControl-Transfer Instructions CTIs Control transfer CTIFloating-Point Operate FPop Instructions Implementation-Dependent InstructionsProcessor Pipeline Instruction Fetch StagesBrhis Issue Stages Execution StagesExecution Stages for Cache Access Completion StagesProcessor States, Normal and Special Traps TrapsPlease refer to .1 of Commonality REDstate Trap Table ErrorstateREDstate REDstate Execution EnvironmentDeferred Traps Reset TrapsTrap Categories Uses of the Trap CategoriesPIL Control Trap ControlTrap-Table Entry Addresses Trap Type TTDetails of Supported Traps Trap ProcessingException and Interrupt Descriptions Sparc JPS1 Implementation-Dependent TrapsPage Memory Models Sparc V9 Memory Model onSparc V9 Memory Model Mode ControlOverview Synchronizing Instruction and Data MemoryRelease 1.0, 1 July Memory Models Page Instruction Definitions SPARC64 V Extensions Table A-1Implementation-Specific InstructionsPage Block Load and Store Instructions VIS Invalid Valid Call and Link Implementation-Dependent InstructionsFloating-Point Multiply-Add/Subtract FormatPage Non-Trapping aexc When FSR.NS = Non-Trapping cexc When FSR.NS =Operation, and inexact, respectively Exceptions fpdisabled Jump and LinkLoad Quadword, Atomic Physical Format 3 LddaMemory Barrier Order Constraints Imposed by mmask Bits Bits in the cmask FieldPrefetch Data Partial Store VIS01816 Table A-7describes prefetch variants implemented in SPARC64 Read State RegisterTable A-7Prefetch Variants Deprecated Instructions Write State RegisterStore Barrier Page Ieee Std 754-1985 Requirements for Floating-Point Nonstandard ModeTraps Inhibiting Results Fpexceptionother Exception ftt=unfinishedFPop Generates an unfinishedFPop exception Denormalized number, eres is less than zeroUnfinishedFPop Boundary Conditions Pessimistic Zero Table B-2unfinishedFPop Boundary ConditionsTable B-3Conditions for a Pessimistic Zero Operation Under FSR.NS =Pessimistic Overflow Table B-4Pessimistic Overflow ConditionsFloating-Point Exceptional Conditions and Results UnfinishedFPop4Nonarithmetic Operations Under FSR.NS = Yes and op2 Nv, dNaNPage Definition of an Implementation Dependency Implementation DependenciesPlease refer to Section C.1 of Commonality List of Implementation Dependencies Hardware CharacteristicsImplementation Dependency Categories Please refer to Section C.2 of CommonalityTable C-1SPARC64 V Implementation Dependencies Errorstate processor state Reset trapEntering errorstate on implementation-dependent errors Deferred trapsFlush instruction Data access FPU trapClean windows trap Floating-point underflow detectionIMPDEPn instructions SIRenable control flagMMU disabled prefetch behavior Unimplemented LDD trapCoherence and atomicity of memory operations Implicit ASI when TLUnimplemented values for PSTATE.MM Implementation-dependent memory modelTable C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 257 255256 258Formal Specification of the Memory Models Please refer to Appendix D of CommonalityPage Opcode Maps Instruction65Page Memory Management Unit Virtual Address TranslationTranslation Table Entry TTE Table F-1Organization of SPARC64 V TLBsRelease 1.0, 1 July Chapter F Memory Management Unit TSB Pointer Formation TSB OrganizationTSB Pointer Formation Faults and Traps TLB miss 64 16-67Instructionaccessexception Reset, Disable, and REDstate Behavior Internal Registers and ASI operations Accessing MMU RegistersAccess Modes Supervisor read/write Asimcntl Memory Control RegisterRMD 10.4 I/D TLB Data In, Data Access, and Tag Read RegistersTable F-3MCNTL Field Description JPS1TSBPPage Table F-4MMU TLB Data Access Address Assignment TLB#MMU TLB Tag Access Register Kbyte page entry10.7 I/D TSB Extension Registers 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSRMMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR TSB Base RegistersTable F-5I-SFSRBit Description EIDTable F-6describes the field encoding for ISFSR.FT FT60 Error DescriptionSFSRBit Description Isfsr Update Policy Table F-8D-SFSRBit Description 1Table F-8D-SFSRBit Description 2 Table F-9defines the encoding of the FT60 field SFSRBit Description 3Dsfsr Update Policy MMU Synchronous Fault Status Register FT Fault Type FieldFresh fault or miss3 Kbytes Table F-10DSFSR Update PolicyMMU Bypass Table F-11Bypass Attribute Bits on SPARC64Automatic TLB Replacement Rule TLB Replacement PolicyRestriction of sTLB Entry Direct Replacement Page Assembly Language Syntax Please refer to Appendix G of CommonalityPage Software Considerations Please refer to Appendix H of CommonalityPage Extending the Sparc V9 Architecture Please refer to Appendix I of CommonalityPage Changes from Sparc V8 to Sparc Please refer to Appendix K of CommonalityPage Programming with the Memory Models Please refer to Appendix J of CommonalityPage SPARC64 V ASI Assignments Address Space IdentifiersSPARC64 V ASI Assignments 1 SPARC64 V ASI Assignments 2 TBDSpecial Memory Access ASIs SPARC64 V ASI Assignments 3Block Load and Store ASIs Partial Store ASIsInterface Definition Barrier Assist for Parallel ProcessingHigh-Speed Lbsy Read Mechanism High-Speed BST Write Mechanism ASI RegistersLbsy Control Register ASICLBSYR0, ASICLBSYR1 Bstw Control Register ASICBSTW0, ASICBSTW1 Bstw Busy Status Register AsicbstwbusyEF16 Last Barrier Synchronization Status Read ASILBSYR0Barrier State Write ASIBSTW0, ASIBSTW1 Read Write is ignoredCache Organization Cache TypesTable M-1L1I Cache Characteristics Level-1 Instruction Cache L1I CacheLevel-1 Data Cache L1D Cache Table M-2L1D Cache CharacteristicsTable M-3L2 Cache Characteristics Level-2 Unified Cache L2 CacheTable M-4Relationships Between Cache Coherency Protocols Cache Coherency ProtocolsCache Control/Status Instructions Table M-5L2 Cache Moesi StatesFlush Level-1 Instruction Cache ASIFLUSHL1ILevel-2 Cache Control Register ASIL2CTRL 3 L2 Diagnostics Tag ReadTable M-6ASIL2CTRL Register Bits 4 L2 Diagnostics Tag Read Registers ASIL2DIAGTAGREADREGPage Interrupt Handling Interrupt DispatchMembar Interrupt Receive Figure N-2is an example of the interrupt receive flowInterrupt Vector Dispatch Register Interrupt Global RegistersInterrupt-Related ASR Registers Interrupt Vector Dispatch Status RegisterPower-on Reset POR Reset, REDstate, and errorstateReset Types Appendix contains these sectionsExternally Initiated Reset XIR Watchdog Reset WDRSoftware-Initiated Reset SIR REDstate and errorstate Figure O-1illustrates the processor state transition diagramPA = 000007FFF000000016 Integer registers Processor State after Reset and in REDstateCPU Fatal Error state Floating Point registersTBA6315 Mask dependentASI Register State After Reset and in REDstate 1 Table O-2ASR State after Reset and in REDstateCounter ASI Register State After Reset and in REDstate 2 OthersASI Register State After Reset and in REDstate 3 Operating Status Register Opsr 11011 UnchangedFirmware Initialization Sequence Hardware Power-On Reset SequenceTo be defined later Page Error Classification Error HandlingFatal Error Urgent Error Errorstate Transition ErrorInstruction-Obstructing Error Urgent Error Independent of Instruction Execution Traps for Urgent Errors Restrainable ErrorCorrectable Error CE, corrected by hardware Following registers are related to the error handling Action and Error ControlRegisters Related to Error Handling Table P-1Registers Related to Error HandlingTable P-2summarizes what happens when an error is detected Summary of Actions Upon Error DetectionTable P-2Action Upon Detection of an Error 1 Ideal specification Table P-2Action Upon Detection of an Error 2Deviation in SPARC64 Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Error Marking for Cacheable DataTable P-3Syndrome for Data Marked for Error Format of Error-Marking DataTable P-4Format of Error-Marked Data Table P-6shows the Errormarkid set by the CPU Table P-5ERRORMARKID Bit DescriptionDifference Between Error Marking on SPARC64 IV Table P-7Error Marking on SPARC64 IV and SPARC64Table P-8 Asieidr Bit Description Control of Error Action AsierrorcontrolValue in ASIERRORCONTROL, as defined in Table P-9 RteueWeaked Ugehandler4C16 Fatal Error and errorstate Transition ErrorTable P-10Format of Asistchgerrorinfo Bit Description Always 0 EeotherTypes of errorstate Transition Errors Fatal Error TypesCurrent SPARC64 V implementation Ideal specification not implemented Urgent ErrorTable P-11ASIUGESR Bit Description 1 Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Table P-11ASIUGESR Bit Description 4 Action of asyncdataerror ADE TrapConditions that cause ADE trap Instend Priv Mugedae Mugeiae MugeiugeFollowing actions are executed in this order Set the specific register settingFollowing three sets of registers are updated State transitionUpon completion of a Retry or Done instruction Update of ASIUGESR, as shown in Table P-13Instruction End-Method at ADE Trap InstendExpected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap Data Access Errors Instruction Access ErrorsSee Appendix F, Memory Management Unit, for details Restrainable Errors Asiasyncfaultstatus AsiafsrDGL1$U2$STLB CeincomedUERAWL2$INSD UedstbetoUERAWL2$FILL Implementation Deviation SPARC64 V setsContents WAYASIASYNCFAULTADDRU2 register is described in Table P-17 SyndromeExpected Software Handling of Restrainable Errors Contents of PABIT423Page Table P-18shows error handling for most registers Handling of Internal Register ErrorsRegister Error Handling Excluding ASRs and ASI Registers Terminology used in Table P-18is defined as followsTable P-19ASR Error Handling ASR Error HandlingTable P-19shows the handling of ASR errors ADE trap, WTerminology used in Table P-20is defined as follows ASI Register Error HandlingError Protect Parity AlwaysError Detect Condition Error Type CorrectionTable P-20shows the handling of ASI register errors Table P-20Handling of ASI Register ErrorsTable P-20Handling of ASI Register Errors SPARC64 V Implementation and the Ideal Specification Cache Error HandlingHandling of a Cache Tag Error Error in D1 Cache Tag and I1 Cache TagError in U2 Unified Level 2 Cache Tag Handling of a D1 Cache Data Error Handling of an I1 Cache Data ErrorCorrectable Error in D1 Cache Data Marked Uncorrectable Error in D1 Cache Data Marked Uncorrectable Error in U2 Cache Data Handling of a U2 Cache Data ErrorCorrectable Error in U2 Cache Data Raw Uncorrectable Error in U2 Cache DataWay Reduction Condition Automatic Way Reduction of I1 Cache, D1 Cache, and U2 CacheI1 Cache Way Reduction D1 Cache Way Reduction U2 Cache Way ReductionError in TLB Entry Detected on Ldxa Instruction Access TLB Error HandlingHandling of TLB Entry Errors Table P-22Error Protection and Detection of TLB EntriesAutomatic Way Reduction of sTLB Handling of Extended UPA Data Bus Error Handling of Extended UPA Bus Interface ErrorHandling of Extended UPA Address Bus Error STLB Way ReductionCorrectable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Sample Pseudocodes Performance InstrumentationPerformance Monitor Overview Counter Clear/SetCounter Event Selection and Start Counter Stop and ReadPerformance Monitor Description Table Q-1Events and Encoding of Performance MonitorInstruction Statistics Events and Encoding of Performance MonitorInstruction Count instructioncounts Counts the committed Floating Multiply-and-Add instructionsTrap-Related Statistics Counts the occurrences of instruction uTLB misses MMU Event CountersCounts the occurrences of Tcc instructions Counts the occurrences of data uTLB missesCounts the occurrences of D1 cache misses Cache Event CountersCounts the occurrences of I1 cache misses Counts the total latency of I1 cache missesCounts the occurrences of L2 cache miss by demand access Counts L2 cache references by demand read accessCounts the number of Scpireq packets received UPA Event CountersCounts the number of Sinvreq packets received Counts the number of Scpbreq packets receivedMiscellaneous Counters Barrier-Assist ASI Read Count asirdbarPage Table R-1shows the mapping of the CPU’s UPA port slave area UPA Programmer’s ModelMapping of the CPU’s UPA Port Slave Area Table R-1CPU’s UPA Port Slave Area MappingUPA PortID Register Table R-2UPA PortID Register FieldsUPA PortID Register Fields UPA Config RegisterTable R-3UPA Config Register Description UpacapUPA Config Register Description MID PconUPCCAP2 UpccapPage Summary of Differences between SPARC64 V and UltraSPARC-III SPARC64 V and UltraSPARC-III Differences 1Table T-1SPARC64 V and UltraSPARC-III Differences 2 UPATable T-1SPARC64 V and UltraSPARC-III Differences 3 SfsrPage General References BibliographyPlease refer to Bibliography in Commonality Page Index AugePage ASIINTRW133 Page Error detection action155 DAEDGL1$L2$STLB error194 DGL1$U2$STLB error195 On Jmpl instruction error53 update during MMU trap90 DmmuECCerror exception46, 153, 155 Persistence38Statistics monitoring206-207 FQ17 FSRImmu Update during MMU trap90 IsfsrLddfa instruction80 PSO41 RMO41OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB Way reduction194 uDTLB10, 85 UITLB10, 85, 90 uncorrectable error152UnimplementedFPop floating-point trap type70