Fujitsu Fujitsu SPARC64 V manual Table C-1SPARC64 V Implementation Dependencies 9

TABLE C-1SPARC64 V Implementation Dependencies (9 of 11)

Nbr	SPARC64 V Implementation Notes	Page
227	TSB number of entries	88
	SPARC64 V supports a maximum of 16 million entries in the common TSB
	and a maximum of 32 million lines the Split TSB.
228	TSB_Hash supplied from TSB or context-ID register	88
	TSB_Hash is generated from the context-ID register in SPARC64 V.
229	TSB_Base address generation	88
	SPARC64 V generates the TSB_Base address directly from the TLB
	Extension Registers. By maintaining compatibility with UltraSPARC I/II,
	SPARC64 V provides mode flag MCNTL.JPS1_TSBP. When
	MCNTL.JPS1_TSBP = 0, the TSB_Base register is used.
230	data_access_exception trap	89
	SPARC64 generates data_access_exception only for the causes listed in
	Section 7.6.1 of Commonality.
231	MMU physical address variability	91
	SPARC64 V supports both 41-bit and 43-bit physical address mode. The
	initial width of the physical address is controlled by OPSR.
232	DCU Control Register CP and CV bits	23, 91
	SPARC64 V does not implement CP and CV bits in the DCU Control
	Register. See also impl. dep. #226.
233	TSB_Hash field	92
	SPARC64 V does not implement TSB_Hash.
234	TLB replacement algorithm	93
	For fTLB, SPARC64 V implements a pseudo-LRU. For sTLB, LRU is used.
235	TLB data access address assignment	94
	The MMU TLB data-access address assignment and the purpose of the
	address are implementation dependent.
236	TSB_Size field width	97
	In SPARC64 V, TSB_Size is 4 bits wide, occupying bits 3:0 of the TSB
	register. The maximum number of TSB entries is, therefore, 512 ⋅	215 (16M
	entries).
237	DSFAR/DSFSR for JMPL/RETURN mem_address_not_aligned	89, 97
	A mem_address_not_aligned exception that occurs during a JMPL or RETURN
	instruction does not update either the D-SFARor D-SFSRregister.
238	TLB page offset for large page sizes	87
	On SPARC64 V, even for a large page, written data for TLB Data Register is
	preserved for bits representing an offset in a page, so the data previously
	written is returned regardless of the page size.
239	Register access by ASIs 5516 and 5D16	92

In SPARC64 V, VA<63:19> of IMMU ASI 5516 and DMMU ASI 5D16 are ignored. An access to virtual addresses 4000016 to 60FF816 is treated as an access 0000016 to 20FF816

78 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002