Fujitsu Fujitsu SPARC64 V manual Flush instruction, Data access FPU trap, Maximum trap level

TABLE C-1SPARC64 V Implementation Dependencies		(4 of 11)
Nbr	SPARC64 V Implementation Notes	Page
42	FLUSH instruction	—

SPARC64 V implements the FLUSH instruction in hardware.

43Reserved.

44	Data access FPU trap	—
	The destination register(s) are unchanged if an access error occurs.
45–46	Reserved.
47	RDASR	—
	See A.50, Read State Register, in Commonality for details.
48	WRASR	—
	See A.70, Write State Register, in Commonality for details.
49–54	Reserved.
55	Floating-point underflow detection	—
	See FSR_underflow in Section 5.1.7 of Commonality for details.
56–100	Reserved.
101	Maximum trap level	20
	MAXTL = 5.
102	Clean windows trap	—
	SPARC64 V generates a clean_window exception; register windows are
	cleaned in software.
103	Prefetch instructions	—
	SPARC64 V implements PREFETCH variations 0–3and 20–23 with the
	following implementation-dependent characteristics:

•The prefetches have observable effects in privileged code.

•Prefetch variants 0–3 do not cause a fast_data_access_MMU_miss trap, because the prefetch is dropped when a fast_data_access_MMU_miss condition happens. On the other hand, prefetch variants 20–23 cause data_access_MMU_miss traps on TLB misses.

•All prefetches are for 64-byte cache lines, which are aligned on a 64-byte boundary.

•See Section A.49, Prefetch Data, on page 57, for implemented variations and their characteristics.

•Prefetches will work normally if the ASI is ASI_PRIMARY,

ASI_SECONDARY, or ASI_NUCLEUS, ASI_PRIMARY_AS_IF_USER,

ASI_SECONDARY_AS_IF_USER, and their little-endian pairs.

104	VER.manuf	20
	VER.manuf = 000416. The least significant 8 bits are Fujitsu’s JEDEC
	manufacturing code.
105	TICK register	19
	SPARC64 V implements 63 bits of the TICK register; it increments on every
	clock cycle.

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 73