Fujitsu Fujitsu SPARC64 V manual Table P-11ASIUGESR Bit Description 3

TABLE P-11ASI_UGESR Bit Description (3 of 4)

Bit	Name	RW Description
15	AUG_SDC	R System data corruption. Indicates the occurrence of the following system data
		corruption:
		Small data corruption: Data in the cacheable area with an unpredictable
		address is destroyed. The destroyed area is some number of 64-byte blocks.
		Invalid physical address usage by software: On SPARC64 V, the following
		invalid physical address usage by software causes system data corruption:
		• If a memory access with a physical address ≥ 200_0000_000016 is issued,
		then the 41-bit width for the UPA address is specified in the
		UPA_configuration_register.AM field.
		• A cacheable access with a physical address ≥ 400_0000_000016 was issued.
		Other error with data damage not limited to the CPU: In JPS1, this type of
		error is treated as a fatal error. On SPARC64 V, OPSR selects whether these
		errors cause a fatal error or an AUG_SDC error.
		Some address tag errors in the SPARC64 V data buffer cause AUG_SDC.
14	IUG_WDT	R Watchdog timeout first time. Indicates the first watchdog timeout. If
		IUG_WDT = 1 when a single-ADEtrap occurs, the instruction pointed to by TPC
		is abandoned and its result is unpredictable.
10	IUG_DTLB	R Uncorrectable error in DTLB during load, store, or demap. Indicates that one of
		the following errors was detected during a data TLB access:
		• An uncorrectable error in TLB data or TLB tag was detected when an LDXA
		instruction attempted to read ASI_DTLB_DATA_ACCESS or
		ASI_DTLB_TAG_ACCESS. TPC indicates either the instruction causing the
		error or the previous instruction.
		• A store to the data TLB or a demap of the data TLB failed. TPC indicates
		either the instruction causing the error or the instruction following the one
		that caused the error.
9	IUG_ITLB	R Uncorrectable error in ITLB during load, store, or demap. Indicates that one of
		the following errors was detected during an instruction TLB access:
		• An uncorrectable error in TLB data or TLB tag was detected when an LDXA
		instruction attempted to read ASI_ITLB_DATA_ACCESS or
		ASI_ITLB_TAG_ACCESS. TPC indicates either the instruction causing the
		error or the previous instruction.
		• A store to the instruction TLB or a demap of the instruction TLB failed. TPC
		indicates either the instruction causing the error or the successive
		instruction.
8	IUG_COREERR	R CPU core error. Indicates an uncorrectable error in a CPU internal resource
		used to execute instructions, which cannot be directly accessed by software.

When there is an uncorrectable error in a program-visible register and the instruction reading the register with UE is executed, the error in the register is always indicated. In this case, IUG_COREERR may or may not be indicated simultaneously with the register error.

Release 1.0, 1 July 2002 F. Chapter P Error Handling 167