Fujitsu Fujitsu SPARC64 V manual Table T-1SPARC64 V and UltraSPARC-III Differences 3, Sfsr

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TABLE T-1SPARC64 V and UltraSPARC-III Differences (3 of 3)

 

 

SPARC64 V

 

UltraSPARC-

Feature

SPARC64 V

Page

UltraSPARC-III

III Section

 

 

 

 

 

 

 

 

 

 

Error status

ASI 4C16/0816 (ASI_UGESR):

165

Not implemented.

 

SPARC64 V implements an error

 

 

 

 

status register to indicate where an

 

 

 

 

error was detected.

 

 

 

 

 

 

 

 

Error Control

ASI 4C16/1016(ASI_ECR):

161

Not implemented.

Register

SPARC64 V implements a control

 

 

 

 

register to signal/suppress a trap

 

 

 

 

when an error was detected.

 

 

 

 

 

 

 

 

ASI_AFAR

Multiple registers (VA addressed)

177

Single register, multiple use.

P.4.2

 

for L1D, L2. 43-bit PA.

 

43-bit PA.

 

 

 

 

 

 

ASI device and

ASI 5316: provides an identification

119

ASI 5316: ASI_SERIAL_ID

?

serial ID

code for each processor.

 

 

 

 

 

 

 

 

I/D SFSR

Many differences.

97

Many differences.

Chapter 8

 

 

 

 

 

Error

ASI 6E16: SPARC64 V implements

161

Not implemented.

Identification

an error ID register. Used to encode

 

 

 

Register (EIDR)

CPU-ID into error marking when

 

 

 

 

an unrecoverable ECC error occurs.

 

 

 

 

 

 

 

 

I-cache and

Not supported.

ASIs 6616 through 6816 and ASI

V.4, V.5

Branch

 

 

6F16 support instruction cache

 

Prediction Array

 

 

and branch prediction array

 

 

 

 

diagnostic access.

 

 

 

 

 

 

MCU Control

SPARC64 V does not have an

ASI 7216: MCU Control Register.

App. U

Register

MCU.

 

 

 

 

 

 

 

 

Module ID bits

Implements 5-bit IDs.

136

Implements 10-bit IDs.

R.2

 

 

 

 

 

Performance

SPARC64 V implements a different

203

UltraSPARC-III implements a

App. Q

counters

set of performance counters than

 

different set of performance

 

 

those of UltraSPARC-III.

 

counters than those of

 

 

 

 

SPARC64 V.

 

 

 

 

 

 

Dispatch

SPARC64 V does not have the DCR.

22

UltraSPARC-III defines the DCR.

5.2.11

Control Register

 

 

 

 

(DCR)

 

 

 

 

 

 

 

 

 

Version Register

For SPARC64 V:

20

For UltraSPARC-III:

C.3.4

(VER)

manuf = 000416,

 

manuf = 001716,

 

 

impl = 5,

 

impl = 001416,

 

 

mask = <mask revision number>,

 

mask = <mask revision number>,

 

 

maxtl = 5,

 

maxtl = 5,

 

 

maxwin = 7.

 

maxwin = 7.

 

 

 

 

 

 

Watchdog reset

Supports watchdog_reset trap. By

140

Supports watchdog_reset trap.

O.1

trap

setting OPSR, watchdog_reset trap

 

 

 

 

is not signalled and CPU stays in

 

 

 

 

error_state.

 

 

 

 

 

 

 

 

Release 1.0, 1 July 2002

F. Chapter S Summary of Differences between SPARC64 V and UltraSPARC-III 221

Page 232
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Fujitsu Fujitsu SPARC64 V manual Table T-1SPARC64 V and UltraSPARC-III Differences 3, Sfsr