Fujitsu Fujitsu SPARC64 V manual Handling of Extended UPA Bus Interface Error, STLB Way Reduction

sTLB Way Reduction

When a way reduction condition is recognized for the sTLB way W (W = 0 or 1), hardware executes the following way reduction procedures:

1.When only one way in sTLB is active because of previous way reductions:

■The previously reduced way is reactivated.

2.Regardless of how many ways were previously active, way reduction occurs:

■Hardware reduces the way and invalidates all entries in sTLB way W. Way W will never be refilled.

■The restrainable error ASI_AFSR.DG_L1$U2$STLB is reported to software.

P.11 Handling of Extended UPA Bus Interface Error

This section specifies how SPARC64 V handles UPA address and data bus errors.

P.11.1 Handling of Extended UPA Address Bus Error

The extended UPA address bus is protected by a parity bit attached to every 8 bits.

When the SPARC64 V processor detects a parity error in the extended UPA address bus, the processor takes one of the following actions, depending on the OPSR setting:

1.Upon detection of the error, the processor enters the CPU fatal error state.

2.Upon detection of the autonomous urgent error ASI_UGESR.AUG_SDC, the processor tries to continue running. However, in some situations, the processor detects a fatal error and enters the CPU fatal error state.

P.11.2 Handling of Extended UPA Data Bus Error

The extended UPA data bus is protected by a single-bit error correction and double- bit error detection ECC code attached to every doubleword.

Error marking is applied to the data transmitted through the extended UPA data bus. The SPARC64 V processor will detect the following three types of errors at the extended UPA data bus interface:

■Correctable error (1-bit error)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 197