Fujitsu Fujitsu SPARC64 V manual Block Load and Store ASIs, Partial Store ASIs

ASI 4F16 (ASI_SCRATCH_REGx)

SPARC64 V provides eight of 64-bit registers that can be used temporary storage for supervisor software.

Data<63:0>

[1]Register Name: ASI_SCRATCH_REGx (x = 0–7)

[2]	ASI:	4F16
[3]	VA:	VA<5:3> = register number
		The other VA bits must be zero.
[4]	RW:	Supervisor read/write

Block Load and Store ASIs

ASIs E016 and E116 exist only for use with STDFA instructions as Block Store with Commit operations (see Block Load and Store Instructions (VIS I) on page 47). Neither ASI E016 nor ASI E116 should be used with LDDFA; however, if either is used, the LDDFA behaves as follows:

1.No exception is generated based on the destination register rd (impl. dep. #255).

2.For LDDFA with ASI E016 or E11 and a memory address aligned on a 2n-byte boundary, a SPARC64 V processor behaves as follows (impl. dep. #256):

n ≥ 3 (≥ 8-byte alignment): no exception related to memory address alignment is generated, but a data_access_exception is generated (see case 3, below).

n = 2 (4-byte alignment): LDDF_mem_address_not_aligned exception is generated.

n ≤ 1 (≤ 2-byte alignment): mem_address_not_aligned exception is generated.

3.If the memory address is correctly aligned, a data_access_exception with an AFSR.FTYPE = “invalid ASI” is generated.

Partial Store ASIs

ASIs C016–C516and C816–CD16exist for use with the STDFA instruction for Partial Store operations (see Partial Store (VIS I) on page 57). None of these ASIs should be used with LDDFA; however, if one of them is used, the LDDFA behaves as follows on a SPARC64 V processor (impl. dep. #257):

1.For LDDFA with C016–C516or C816–CD16and a memory address aligned on a 2n- byte boundary, a SPARC64 V processor behaves as follows:

n ≥ 3 (≥ 8-byte alignment): no exception related to memory address alignment is generated.

120 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002