Fujitsu Fujitsu SPARC64 V manual Uedstbeto, UERAWL2$FILL, UERAWL2$INSD, UERAWD1$INSD

TABLE P-15ASI_ASYNC_FAULT_STATUS Bit Description (Continued)

Bit	Name	R/W	Prio_D1	Prio_U2	Description
3	UE_DST_BETO	RW1C			Disrupting store UPA bus error or timeout. Indicates
					that the store data is not written to memory because
					one of following errors was detected after the store
					instruction completed:
					• UPA bus error for the store instruction — Detected
					when a cacheable store to a noncacheable area is
					executed.
					• UPA timeout for a store instruction — Detected
					when a cacheable store to an uninstalled cacheable
					area is executed.
2	UE_RAW_L2$FILL	RW1C		8016	Raw UE in incoming data at L2 cache fill. Indicates a
					raw (unmarked) uncorrectable error in incoming data
					from UPA bus at the level 2 cache fill. The
					doubleword containing the raw UE in the L2 cache
					was marked with the ERROR_MARK_ID = 0.
1	UE_RAW_L2$INSD	RW1C		C016	Raw UE in L2 cache inside data. Indicates that a raw
					(unmarked) uncorrectable error in the L2 cache data
					is detected. The raw UE error should be detected in
					the following cases:
					• L2 cache data is read to fill D1 cache or I1 cache.
					• L2 cache data is read for copyback or writeback.
					The doubleword containing the raw UE in the read
					data and the doubleword in the L2 cache data are
					marked with ERROR_MARK_ID = ASI_EIDR.
					Implementation Deviation: SPARC64 V sets
					UE_RAW_L2$INSD to 1 only when a raw UE is
					detected during L2 cache writeback.
0	UE_RAW_D1$INSD	RW1C	8016		Raw UE in D1 cache inside data. This bit indicates
					that a raw (not marked) uncorrectable error in the D1
					cache data has been detected in one of the following
					cases:
					• D1 cache data is read during a load or store
					instruction.
					• Store data is not written because of an
					uncorrectable error detected in the D1 cache after
					the store instruction completed.
					• A raw UE is detected in the data during the D1
					cache writeback to level 2 cache.
					The doubleword containing a raw UE in the outgoing
					data and that in D1 cache are marked with
					ERROR_MARK_ID = ASI_EIDR.
Other	Reserved	R			Always reads as 0; writes are ignored.

176 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002