Fujitsu Fujitsu SPARC64 V 255, 256, 257, 258, Table C-1SPARC64 V Implementation Dependencies 11

TABLE C-1SPARC64 V Implementation Dependencies (11 of 11)

Nbr	SPARC64 V Implementation Notes	Page
252	DCUCR.DC (Data Cache Enable)	24
	SPARC64 V does not implement DCUCR.DC.
253	DCUCR.IC (Instruction Cache Enable)	24
	SPARC64 V does not implement DCUCR.IC.
254	Means of exiting error_state	37, 146
	The standard behavior of a SPARC64 V CPU upon entry into
	error_state is to reset itself by internally generating a watchdog_reset
	(WDR). However, OPSR can be set so that when error_state is entered, the
	processor remains halted in error_state instead of generating a
	watchdog_reset.
255	LDDFA with ASI E016 or E116 and misaligned destination register number	120
	No exception is generated based on the destination register rd.
256	LDDFA with ASI E016 or E116 and misaligned memory address	120
	For LDDFA with ASI E016 or E11 and a memory address aligned on a 2n-byte

boundary, a SPARC64 V processor behaves as follows:

n ≥ 3 (≥ 8-byte alignment): no exception related to memory address alignment is generated.

n= 2 (4-byte alignment): LDDF_mem_address_not_aligned exception is

generated.

n ≤ 1 (≤ 2-byte alignment): mem_address_not_aligned exception is generated.

257	LDDFA with ASI C016–C516or C816–CD16and misaligned memory address	120
	For LDDFA with C016–C516or C816–CD16and a memory address aligned on
	a 2n-byte boundary, a SPARC64 V processor behaves as follows:
	n ≥ 3 (≥ 8-byte alignment): no exception related to memory address
	alignment is generated.
	n = 2 (4-byte alignment): LDDF_mem_address_not_aligned exception is
	generated.
	n ≤ 1 (≤ 2-byte alignment): mem_address_not_aligned exception is
	generated.
258	ASI_SERIAL_ID	119
	SPARC64 V provides an identification code for each processor.

80 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002