Fujitsu Fujitsu SPARC64 V manual Table T-1SPARC64 V and UltraSPARC-III Differences 2, Upa

TABLE T-1SPARC64 V and UltraSPARC-III Differences (2 of 3)

		SPARC64 V		UltraSPARC-
Feature	SPARC64 V	Page	UltraSPARC-III	III Section
Floating-point	In general, SPARC64 V does not	65	In general, UltraSPARC-III does	B.6.1
subnormal	handle most subnormal operands		not handle most subnormal
handling	and results in hardware. However,		operands and results in
	its handling differs from that of		hardware. However, its handling
	UltraSPARC-III.		differs from that of SPARC64 V.
Block LD/ST	SPARC64 V maintains register	47	UltraSPARC-III does not	A.4
implementation	dependency between block load/		necessarily preserve memory or
	store and other instructions, but		register dependency ordering in
	hardware memory order constraint		block load/store operations.
	is less than TSO.
PREFETCH(A)	Prefetch-invalidate is not	57	Implements prefetch-invalidate	A.49.1
implementation	implemented—SPARC64 V does		(fcn = 16).
	not implement a P-cache.		fcn = 20-23 does not cause a
	Prefetch with fcn = 20-23 causes a		trap. Equivalent to fcn = 0-3.
	trap on mDTLB miss.
Data cache	Because SPARC64 V supports	—	Because the data cache uses one	1.4.4, M.2
flushing	unaliasing by hardware, a flush of		virtual address bit for indexing, a
	data cache is not needed.		displacement flushing algorithm
			or a cache diagnostic write is
			required when a virtual address
			alias is created.
TPC/TNPC state	Both TPC and TNPC values are	141	TPC<5:0> is zero after any reset	C.2.5
after power-on	undefined after a power-on reset.		trap. TNPC will be equal to
reset			TNPC+4.
W-cache	SPARC64 V does not support a W-	117	ASIs 3816–3B16provide	L.3.2
	cache.		diagnostic access to the W-cache.
P-cache	SPARC64 V does not support a	117	ASIs 3016–3316provide diagnostic	L.3.2
	P-cache.		access to the P-cache.
UPA	SPARC64 V uses ASI 4A16 as the	215	UltraSPARC-III does not support	R.2
Configuration	UPA configuration register.		UPA. Fireplane configuration
ASI			register is assigned in ASI 4A16.
SRAM test init	Not supported.	—	ASI 4016: not defined in manual.	—
D-cache	Not supported.	—	ASIs 4216 through 4716 support	L.3.2
			data cache diagnostic access.
E-cache	ASIs 6B16 and 6C16 support E-	130	ASIs 4B16, 4E16, 7416, 7516, 7616,	L.3.2
	cache diagnostic access.		and 7E16 support control over the
			E-cache.
ASI_AFSR	Many differences.	174	Many differences.	P.4.2

220 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002