Fujitsu Fujitsu SPARC64 V manual Action and Error Control, Registers Related to Error Handling

ECC_error

■Degradation

SPARC64 V can isolate an internal hardware resource that generates frequent errors and continue processing without deleterious effect on software during program execution. However, performance is degraded by the resource isolation. This degradation is reported as a restrainable error.

The restrainable error can be reported to privileged software by the ECC_error trap.

When PSTATE.IE = 1 and the trap enable mask for any restrainable error is 1, the exception is generated for the restrainable error.

P.2 Action and Error Control

P.2.1 Registers Related to Error Handling

The following registers are related to the error handling.

■ASI registers: Indicate an error. All ASI registers in TABLE P-1except ASI_EIDR and ASI_ERROR_CONTROL are used to specify the nature of an error to privileged software.

■ASI_ERROR_CONTROL: Controls error action. This register designates error detection masks and error trap enable masks.

■ASI_EIDR: Marks errors. This register identifies the error source ID for error marking.

TABLE P-1lists the registers related to error handling.

TABLE P-1Registers Related to Error Handling

ASI	VA	R/W	Checking Code	Name	Defined in
4C16	0016	RW1C	None	ASI_ASYNC_FAULT_STATUS	P.7.1
4C16	0816	R	None	ASI_URGENT_ERROR_STATUS	P.4.1
4C16	1016	RW	Parity	ASI_ERROR_CONTROL	P.2.1
4C16	1816	R,W1AC	None	ASI_STCHG_ERROR_INFO	P.3.1
4D16	0016	RW1AC	Parity	ASI_ASYNC_FAULT_ADDR_D1	P.7.2
4D16	0816	RW1AC	Parity	ASI_ASYNC_FAULT_ADDR_U2	P.7.3
5016	1816	RW	None	ASI_IMMU_SFSR	F.10.9
5816	1816	RW	None	ASI_DMMU_SFSR	F.10.9
5816	2016	RW	Parity	ASI_DMMU_SFAR	F.10.10 of Commonality
6E16	0016	RW	Parity	ASI_EIDR	P.2.5

Release 1.0, 1 July 2002 F. Chapter P Error Handling 153