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Fujitsu Fujitsu SPARC64 V manual Instruction Prefetch

Models: Fujitsu SPARC64 V

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1.If a memory operation y resolves to a volatile memory address (location[y]), SPARC64 V will not speculatively prefetch location[y] for any reason; location[y] will be fetched or stored to only when operation y is commitable.

2.If a memory operation y resolves to a nonvolatile memory address (location[y]), SPARC64 V may speculatively prefetch location[y] subject, adhering to the following subrules:

a.If an operation y can be speculatively prefetched according to the prior rule, operations with store semantics are speculatively prefetched for ownership only if they are prefetched to cacheable locations. Operations without store semantics are speculatively prefetched even if they are noncacheable as long as they are not volatile.

b.Atomic operations (CAS(X)A, LDSTUB, SWAP) are never speculatively prefetched.

SPARC64 V provides two mechanisms to avoid speculative execution of a load:

1.Avoid speculation by disallowing speculative accesses to certain memory pages or I/O spaces. This can be done by setting the E (side-effect) bit in the PTE for all memory pages that should not allow speculation. All accesses made to memory pages that have the E bit set in their PTE will be delayed until they are no longer speculative or until they are cancelled. See Appendix F, Memory Management Unit, for details.

2.Alternate space load instructions that force program order, such as

ASI_PHYS_BYPASS_WITH_EBIT[_L] (AS I = 1516, 1D16), will not be speculatively executed.

6.1.2Instruction Prefetch

The processor prefetches instructions to minimize cases where the processor must wait for instruction fetch. In combination with branch prediction, prefetching may cause the processor to access instructions that are not subsequently executed. In some cases, the speculative instruction accesses will reference data pages. SPARC64 V does not generate a trap for any exception that is caused by an instruction fetch until all of the instructions before it (in program order) have been committed.1

1.Hardware errors and other asynchronous errors may generate a trap even if the instruction that caused the trap is never committed.

26 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

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Fujitsu Fujitsu SPARC64 V manual Instruction Prefetch

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Traps InstructionsMemory Models Sparc JPS1 Implementation-Dependent TrapsImplementation Dependencies Level-1 Instruction Cache L1I Cache Cache Organization 125 Cache TypesError Handling 149 Error Classification Reset, REDstate, and errorstate 137 Reset TypesFatal Error Asistchgerrorinfo General References UPA Programmer’s ModelIndex Page Navigating the SPARC64 V Implementation Supplement OverviewFonts and Notational Conventions Microarchitecture for High Performance SPARC64 V processorHigh Integration High Reliability and High IntegrityAdvanced RAS features for the core Advanced RAS features for cachesExtended RAS interface to software Component Overview Asynchronous data error ADE trap for additional errorsSX-Unit Execution Unit EU Instruction Control Unit IU1Instruction Control Unit Major Blocks 2Execution Unit Major BlocksStorage Unit Major Blocks Storage Unit SU4Secondary Cache and External Access Unit Major Blocks Secondary Cache and External Access Unit SXUInstruction dispatch Synonym instruction initiation DefinitionsIssue-stalling Sync Synonym machine sync Page Architectural Overview Page Please refer to , Data Formats in Commonality Data FormatsPage Nonprivileged Registers RegistersFSRnonstandardfp NS Floating-Point State Register FSRFSRversion ver FSRfloating-pointtraptype fttTick Tick Register Privileged RegistersTrap State Tstate Register FSR ConformanceAncillary State Registers ASRs Version VER RegisterPerformance Control Register PCR ASR 1shows the values for the VER register for SPARC64Ovro OVFRegisters Referenced Through ASIs Accessibility as described above impl. dep. #250Performance Instrumentation Counter PIC Register ASR Dispatch Control Register DCR ASRVM70 PM70IU Deferred-Trap Queue Floating-Point Deferred-Trap Queue FQData Watchpoint Registers Instruction Trap RegisterInstruction Execution InstructionsData Prefetch Instruction Prefetch 1SPARC64 V Syncing Instructions Syncing Instructions2Instruction Fields Specific to SPARC64 Instruction Formats and FieldsYes Control-Transfer Instructions CTIs Instruction CategoriesCall and Jmpl Instructions Control transfer CTIImplementation-Dependent Instructions Floating-Point Operate FPop InstructionsInstruction Fetch Stages Processor PipelineBrhis Execution Stages Issue StagesCompletion Stages Execution Stages for Cache AccessProcessor States, Normal and Special Traps TrapsPlease refer to .1 of Commonality REDstate ErrorstateREDstate Trap Table REDstate Execution EnvironmentTrap Categories Reset TrapsDeferred Traps Uses of the Trap CategoriesTrap-Table Entry Addresses Trap ControlPIL Control Trap Type TTException and Interrupt Descriptions Trap ProcessingDetails of Supported Traps Sparc JPS1 Implementation-Dependent TrapsPage Sparc V9 Memory Model on Memory ModelsOverview Mode ControlSparc V9 Memory Model Synchronizing Instruction and Data MemoryRelease 1.0, 1 July Memory Models Page Table A-1Implementation-Specific Instructions Instruction Definitions SPARC64 V ExtensionsPage Block Load and Store Instructions VIS Invalid Valid Implementation-Dependent Instructions Call and LinkFormat Floating-Point Multiply-Add/SubtractPage Non-Trapping aexc When FSR.NS = Non-Trapping cexc When FSR.NS =Operation, and inexact, respectively Jump and Link Exceptions fpdisabledFormat 3 Ldda Load Quadword, Atomic PhysicalMemory Barrier Bits in the cmask Field Order Constraints Imposed by mmask BitsPrefetch Data Partial Store VIS01816 Table A-7describes prefetch variants implemented in SPARC64 Read State RegisterTable A-7Prefetch Variants Deprecated Instructions Write State RegisterStore Barrier Page Ieee Std 754-1985 Requirements for Floating-Point Nonstandard ModeTraps Inhibiting Results Fpexceptionother Exception ftt=unfinishedFPop Generates an unfinishedFPop exception Denormalized number, eres is less than zeroUnfinishedFPop Boundary Conditions Table B-2unfinishedFPop Boundary Conditions Pessimistic ZeroPessimistic Overflow Operation Under FSR.NS =Table B-3Conditions for a Pessimistic Zero Table B-4Pessimistic Overflow ConditionsUnfinishedFPop4 Floating-Point Exceptional Conditions and ResultsYes and op2 Nv, dNaN Nonarithmetic Operations Under FSR.NS =Page Definition of an Implementation Dependency Implementation DependenciesPlease refer to Section C.1 of Commonality Implementation Dependency Categories Hardware CharacteristicsList of Implementation Dependencies Please refer to Section C.2 of CommonalityTable C-1SPARC64 V Implementation Dependencies Entering errorstate on implementation-dependent errors Reset trapErrorstate processor state Deferred trapsClean windows trap Data access FPU trapFlush instruction Floating-point underflow detectionMMU disabled prefetch behavior SIRenable control flagIMPDEPn instructions Unimplemented LDD trapUnimplemented values for PSTATE.MM Implicit ASI when TLCoherence and atomicity of memory operations Implementation-dependent memory modelTable C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 256 255257 258Please refer to Appendix D of Commonality Formal Specification of the Memory ModelsPage Instruction65 Opcode MapsPage Virtual Address Translation Memory Management UnitTable F-1Organization of SPARC64 V TLBs Translation Table Entry TTERelease 1.0, 1 July Chapter F Memory Management Unit TSB Pointer Formation TSB OrganizationTSB Pointer Formation TLB miss 64 16-67 Faults and TrapsInstructionaccessexception Reset, Disable, and REDstate Behavior Access Modes Supervisor read/write Accessing MMU RegistersInternal Registers and ASI operations Asimcntl Memory Control RegisterTable F-3MCNTL Field Description 10.4 I/D TLB Data In, Data Access, and Tag Read RegistersRMD JPS1TSBPPage TLB# Table F-4MMU TLB Data Access Address AssignmentKbyte page entry MMU TLB Tag Access RegisterMMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSR10.7 I/D TSB Extension Registers TSB Base RegistersEID Table F-5I-SFSRBit DescriptionTable F-6describes the field encoding for ISFSR.FT FT60 Error DescriptionSFSRBit Description Table F-8D-SFSRBit Description 1 Isfsr Update PolicyTable F-8D-SFSRBit Description 2 SFSRBit Description 3 Table F-9defines the encoding of the FT60 fieldDsfsr Update Policy MMU Synchronous Fault Status Register FT Fault Type FieldFresh fault or miss3 MMU Bypass Table F-10DSFSR Update PolicyKbytes Table F-11Bypass Attribute Bits on SPARC64Automatic TLB Replacement Rule TLB Replacement PolicyRestriction of sTLB Entry Direct Replacement Page Please refer to Appendix G of Commonality Assembly Language SyntaxPage Please refer to Appendix H of Commonality Software ConsiderationsPage Please refer to Appendix I of Commonality Extending the Sparc V9 ArchitecturePage Please refer to Appendix K of Commonality Changes from Sparc V8 to SparcPage Please refer to Appendix J of Commonality Programming with the Memory ModelsPage SPARC64 V ASI Assignments Address Space IdentifiersSPARC64 V ASI Assignments 1 TBD SPARC64 V ASI Assignments 2SPARC64 V ASI Assignments 3 Special Memory Access ASIsPartial Store ASIs Block Load and Store ASIsInterface Definition Barrier Assist for Parallel ProcessingHigh-Speed Lbsy Read Mechanism High-Speed BST Write Mechanism ASI RegistersLbsy Control Register ASICLBSYR0, ASICLBSYR1 Bstw Busy Status Register Asicbstwbusy Bstw Control Register ASICBSTW0, ASICBSTW1Barrier State Write ASIBSTW0, ASIBSTW1 Last Barrier Synchronization Status Read ASILBSYR0EF16 Read Write is ignoredCache Types Cache OrganizationLevel-1 Instruction Cache L1I Cache Table M-1L1I Cache CharacteristicsTable M-3L2 Cache Characteristics Table M-2L1D Cache CharacteristicsLevel-1 Data Cache L1D Cache Level-2 Unified Cache L2 CacheCache Control/Status Instructions Cache Coherency ProtocolsTable M-4Relationships Between Cache Coherency Protocols Table M-5L2 Cache Moesi StatesASIFLUSHL1I Flush Level-1 Instruction CacheLevel-2 Cache Control Register ASIL2CTRL 3 L2 Diagnostics Tag ReadTable M-6ASIL2CTRL Register Bits ASIL2DIAGTAGREADREG 4 L2 Diagnostics Tag Read RegistersPage Interrupt Dispatch Interrupt HandlingMembar Figure N-2is an example of the interrupt receive flow Interrupt ReceiveInterrupt-Related ASR Registers Interrupt Global RegistersInterrupt Vector Dispatch Register Interrupt Vector Dispatch Status RegisterReset Types Reset, REDstate, and errorstatePower-on Reset POR Appendix contains these sectionsExternally Initiated Reset XIR Watchdog Reset WDRSoftware-Initiated Reset SIR Figure O-1illustrates the processor state transition diagram REDstate and errorstatePA = 000007FFF000000016 CPU Fatal Error state Processor State after Reset and in REDstateInteger registers Floating Point registersMask dependent TBA6315ASI Register State After Reset and in REDstate 1 Table O-2ASR State after Reset and in REDstateCounter Others ASI Register State After Reset and in REDstate 2ASI Register State After Reset and in REDstate 3 11011 Unchanged Operating Status Register OpsrFirmware Initialization Sequence Hardware Power-On Reset SequenceTo be defined later Page Error Classification Error HandlingFatal Error Urgent Error Errorstate Transition ErrorInstruction-Obstructing Error Urgent Error Independent of Instruction Execution Traps for Urgent Errors Restrainable ErrorCorrectable Error CE, corrected by hardware Registers Related to Error Handling Action and Error ControlFollowing registers are related to the error handling Table P-1Registers Related to Error HandlingTable P-2summarizes what happens when an error is detected Summary of Actions Upon Error DetectionTable P-2Action Upon Detection of an Error 1 Ideal specification Table P-2Action Upon Detection of an Error 2Deviation in SPARC64 Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Marking for Cacheable Data ErrorTable P-3Syndrome for Data Marked for Error Format of Error-Marking DataTable P-4Format of Error-Marked Data Table P-5ERRORMARKID Bit Description Table P-6shows the Errormarkid set by the CPUTable P-7Error Marking on SPARC64 IV and SPARC64 Difference Between Error Marking on SPARC64 IVValue in ASIERRORCONTROL, as defined in Table P-9 Control of Error Action AsierrorcontrolTable P-8 Asieidr Bit Description RteueUgehandler WeakedTable P-10Format of Asistchgerrorinfo Bit Description Fatal Error and errorstate Transition Error4C16 Always 0 EeotherTypes of errorstate Transition Errors Fatal Error TypesCurrent SPARC64 V implementation Ideal specification not implemented Urgent ErrorTable P-11ASIUGESR Bit Description 1 Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Conditions that cause ADE trap Action of asyncdataerror ADE TrapTable P-11ASIUGESR Bit Description 4 Instend Priv Mugedae Mugeiae MugeiugeFollowing three sets of registers are updated Set the specific register settingFollowing actions are executed in this order State transitionInstruction End-Method at ADE Trap Update of ASIUGESR, as shown in Table P-13Upon completion of a Retry or Done instruction InstendExpected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap Data Access Errors Instruction Access ErrorsSee Appendix F, Memory Management Unit, for details Asiasyncfaultstatus Asiafsr Restrainable ErrorsCeincomed DGL1$U2$STLBUERAWL2$FILL UedstbetoUERAWL2$INSD Implementation Deviation SPARC64 V setsWAY ContentsSyndrome ASIASYNCFAULTADDRU2 register is described in Table P-17Contents of PABIT423 Expected Software Handling of Restrainable ErrorsPage Register Error Handling Excluding ASRs and ASI Registers Handling of Internal Register ErrorsTable P-18shows error handling for most registers Terminology used in Table P-18is defined as followsTable P-19shows the handling of ASR errors ASR Error HandlingTable P-19ASR Error Handling ADE trap, WError Protect ASI Register Error HandlingTerminology used in Table P-20is defined as follows Parity AlwaysError Detect Condition Correction Error TypeTable P-20Handling of ASI Register Errors Table P-20shows the handling of ASI register errorsTable P-20Handling of ASI Register Errors Handling of a Cache Tag Error Cache Error HandlingSPARC64 V Implementation and the Ideal Specification Error in D1 Cache Tag and I1 Cache TagError in U2 Unified Level 2 Cache Tag Handling of a D1 Cache Data Error Handling of an I1 Cache Data ErrorCorrectable Error in D1 Cache Data Marked Uncorrectable Error in D1 Cache Data Correctable Error in U2 Cache Data Handling of a U2 Cache Data ErrorMarked Uncorrectable Error in U2 Cache Data Raw Uncorrectable Error in U2 Cache DataWay Reduction Condition Automatic Way Reduction of I1 Cache, D1 Cache, and U2 CacheI1 Cache Way Reduction U2 Cache Way Reduction D1 Cache Way ReductionHandling of TLB Entry Errors TLB Error HandlingError in TLB Entry Detected on Ldxa Instruction Access Table P-22Error Protection and Detection of TLB EntriesAutomatic Way Reduction of sTLB Handling of Extended UPA Address Bus Error Handling of Extended UPA Bus Interface ErrorHandling of Extended UPA Data Bus Error STLB Way ReductionCorrectable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Performance Monitor Overview Performance InstrumentationSample Pseudocodes Counter Clear/SetCounter Stop and Read Counter Event Selection and StartTable Q-1Events and Encoding of Performance Monitor Performance Monitor DescriptionEvents and Encoding of Performance Monitor Instruction StatisticsCounts the committed Floating Multiply-and-Add instructions Instruction Count instructioncountsTrap-Related Statistics Counts the occurrences of Tcc instructions MMU Event CountersCounts the occurrences of instruction uTLB misses Counts the occurrences of data uTLB missesCounts the occurrences of I1 cache misses Cache Event CountersCounts the occurrences of D1 cache misses Counts the total latency of I1 cache missesCounts L2 cache references by demand read access Counts the occurrences of L2 cache miss by demand accessCounts the number of Sinvreq packets received UPA Event CountersCounts the number of Scpireq packets received Counts the number of Scpbreq packets receivedBarrier-Assist ASI Read Count asirdbar Miscellaneous CountersPage Mapping of the CPU’s UPA Port Slave Area UPA Programmer’s ModelTable R-1shows the mapping of the CPU’s UPA port slave area Table R-1CPU’s UPA Port Slave Area MappingTable R-2UPA PortID Register Fields UPA PortID RegisterTable R-3UPA Config Register Description UPA Config RegisterUPA PortID Register Fields UpacapUPA Config Register Description UPCCAP2 PconMID UpccapPage SPARC64 V and UltraSPARC-III Differences 1 Summary of Differences between SPARC64 V and UltraSPARC-IIIUPA Table T-1SPARC64 V and UltraSPARC-III Differences 2Sfsr Table T-1SPARC64 V and UltraSPARC-III Differences 3Page General References BibliographyPlease refer to Bibliography in Commonality Page Auge IndexPage ASIINTRW133 Page DAE Error detection action155DGL1$L2$STLB error194 DGL1$U2$STLB error195 Dmmu On Jmpl instruction error53 update during MMU trap90Persistence38 ECCerror exception46, 153, 155Statistics monitoring206-207 FSR FQ17Immu Isfsr Update during MMU trap90PSO41 RMO41 Lddfa instruction80OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB Way reduction194 uDTLB10, 85 UITLB10, 85, 90 uncorrectable error152UnimplementedFPop floating-point trap type70