State transition | Fujitsu Fujitsu SPARC64 V manual

The following actions are executed in this order:

a. State transition

if (TL = MAXTL), the CPU enters error_state and abandons the ADE trap;

else if (CPU is in execution state && (TL = MAXTL − 1)), then the CPU enters RED_state.

b. Trap target address calculation

When the CPU is in execution state, trap target address is calculated by %tba, %tt, and %tl.

Otherwise, the CPU is in RED_state and the trap target address is set to

RSTVaddr + A016.

c. TL is incremented: TL ← TL + 1.

3.Save the old value into TSTATE, TPC, and TNPC.

PSTATE, PC, and NPC immediately before the ADE trap are copied into TSTATE, TPC, and TNPC, respectively. If the copy source register contains an uncorrectable error, the copy target register also contains the UE.

4.Set the specific register setting:

The following three sets of registers are updated:

a.Update and validation of specific registers. Hardware writes the registers listed in TABLE P-12.

TABLE P-12Registers Written for Update and Validation

Register	Condition For Writing	Value Written

PSTATE	Always	AG = 1, MG = 0, IG = 0, IE = 0, PRIV = 1, AM = 0, PEF = 1,
		RED = 0 (or 1 depending on the CPU status), MM = 00, TLE = 0,
		CLE = 0.

PC	Always
nPC	Always
CCR	When the register contains UE
FSR, GSR	When the register contains UE

ADE trap address. ADE trap address + 4. 0.

If either FSR or GSR contains a UE, 0 is written to that register. When 0 is written to FSR and/or GSR upon a single- ADE trap, ASI_UGESR.IUG_%F is set to 1.

CWP, CANSAVE, When the register contains UE	Any register among CWP, CANSAVE, CANRESTORE,
CANRESTORE,	OTHERWIN, and CLEANWIN that contains a UE is written to 0.
OTHERWIN,	When 0 is written to one of these registers upon a single-ADE
CLEANWIN	trap, ASI_UGESR.IUG_PSTATE = 1 is set to 1.

The error(s) in a written register are removed by setting the correct value to the error checking (parity) code during the full write of the register.

Release 1.0, 1 July 2002

F. Chapter P Error Handling 169

Image 180

Fujitsu Fujitsu SPARC64 V Following actions are executed in this order, State transition, Trap target address calculation

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Instructions Traps Sparc JPS1 Implementation-Dependent Traps Memory ModelsImplementation Dependencies Cache Organization 125 Cache Types Level-1 Instruction Cache L1I Cache Reset, REDstate, and errorstate 137 Reset Types Error Handling 149 Error ClassificationFatal Error Asistchgerrorinfo UPA Programmer’s Model General ReferencesIndex Page Overview Navigating the SPARC64 V Implementation SupplementFonts and Notational Conventions SPARC64 V processor Microarchitecture for High PerformanceHigh Integration High Reliability and High Integrity Advanced RAS features for caches Advanced RAS features for the coreExtended RAS interface to software Asynchronous data error ADE trap for additional errors Component Overview SX-Unit Instruction Control Unit IU Execution Unit EU1Instruction Control Unit Major Blocks 2Execution Unit Major Blocks Storage Unit SU Storage Unit Major Blocks Secondary Cache and External Access Unit SXU 4Secondary Cache and External Access Unit Major Blocks Definitions Instruction dispatch Synonym instruction initiation Issue-stalling Sync Synonym machine sync Page Architectural Overview Page Data Formats Please refer to , Data Formats in CommonalityPage Registers Nonprivileged Registers Floating-Point State Register FSR FSRnonstandardfp NSFSRversion ver FSRfloating-pointtraptype ftt Privileged Registers Tick Tick RegisterTrap State Tstate Register FSR Conformance Version VER Register Ancillary State Registers ASRsPerformance Control Register PCR ASR 1shows the values for the VER register for SPARC64 OVF Ovro Accessibility as described above impl. dep. #250 Registers Referenced Through ASIsPerformance Instrumentation Counter PIC Register ASR Dispatch Control Register DCR ASR PM70 VM70 Floating-Point Deferred-Trap Queue FQ IU Deferred-Trap QueueData Watchpoint Registers Instruction Trap Register Instructions Instruction ExecutionData Prefetch Instruction Prefetch Syncing Instructions 1SPARC64 V Syncing Instructions Instruction Formats and Fields 2Instruction Fields Specific to SPARC64Yes Instruction Categories Control-Transfer Instructions CTIsCall and Jmpl Instructions Control transfer CTI Floating-Point Operate FPop Instructions Implementation-Dependent Instructions Processor Pipeline Instruction Fetch Stages Brhis Issue Stages Execution Stages Execution Stages for Cache Access Completion Stages Traps Processor States, Normal and Special TrapsPlease refer to .1 of Commonality Errorstate REDstateREDstate Trap Table REDstate Execution Environment Reset Traps Trap CategoriesDeferred Traps Uses of the Trap Categories Trap Control Trap-Table Entry AddressesPIL Control Trap Type TT Trap Processing Exception and Interrupt DescriptionsDetails of Supported Traps Sparc JPS1 Implementation-Dependent TrapsPage Memory Models Sparc V9 Memory Model on Mode Control OverviewSparc V9 Memory Model Synchronizing Instruction and Data Memory Release 1.0, 1 July Memory Models Page Instruction Definitions SPARC64 V Extensions Table A-1Implementation-Specific InstructionsPage Block Load and Store Instructions VIS Invalid Valid Call and Link Implementation-Dependent Instructions Floating-Point Multiply-Add/Subtract FormatPage Non-Trapping cexc When FSR.NS = Non-Trapping aexc When FSR.NS =Operation, and inexact, respectively Exceptions fpdisabled Jump and Link Load Quadword, Atomic Physical Format 3 Ldda Memory Barrier Order Constraints Imposed by mmask Bits Bits in the cmask Field Partial Store VIS Prefetch Data01816 Read State Register Table A-7describes prefetch variants implemented in SPARC64Table A-7Prefetch Variants Write State Register Deprecated InstructionsStore Barrier Page Floating-Point Nonstandard Mode Ieee Std 754-1985 Requirements forTraps Inhibiting Results Fpexceptionother Exception ftt=unfinishedFPop Denormalized number, eres is less than zero Generates an unfinishedFPop exceptionUnfinishedFPop Boundary Conditions Pessimistic Zero Table B-2unfinishedFPop Boundary Conditions Operation Under FSR.NS = Pessimistic OverflowTable B-3Conditions for a Pessimistic Zero Table B-4Pessimistic Overflow Conditions Floating-Point Exceptional Conditions and Results UnfinishedFPop4 Nonarithmetic Operations Under FSR.NS = Yes and op2 Nv, dNaNPage Implementation Dependencies Definition of an Implementation DependencyPlease refer to Section C.1 of Commonality Hardware Characteristics Implementation Dependency CategoriesList of Implementation Dependencies Please refer to Section C.2 of Commonality Table C-1SPARC64 V Implementation Dependencies Reset trap Entering errorstate on implementation-dependent errorsErrorstate processor state Deferred traps Data access FPU trap Clean windows trapFlush instruction Floating-point underflow detection SIRenable control flag MMU disabled prefetch behaviorIMPDEPn instructions Unimplemented LDD trap Implicit ASI when TL Unimplemented values for PSTATE.MMCoherence and atomicity of memory operations Implementation-dependent memory model Table C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 255 256257 258 Formal Specification of the Memory Models Please refer to Appendix D of CommonalityPage Opcode Maps Instruction65Page Memory Management Unit Virtual Address Translation Translation Table Entry TTE Table F-1Organization of SPARC64 V TLBs Release 1.0, 1 July Chapter F Memory Management Unit TSB Organization TSB Pointer FormationTSB Pointer Formation Faults and Traps TLB miss 64 16-67 Instructionaccessexception Reset, Disable, and REDstate Behavior Accessing MMU Registers Access Modes Supervisor read/writeInternal Registers and ASI operations Asimcntl Memory Control Register 10.4 I/D TLB Data In, Data Access, and Tag Read Registers Table F-3MCNTL Field DescriptionRMD JPS1TSBPPage Table F-4MMU TLB Data Access Address Assignment TLB# MMU TLB Tag Access Register Kbyte page entry 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSR MMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR10.7 I/D TSB Extension Registers TSB Base Registers Table F-5I-SFSRBit Description EID FT60 Error Description Table F-6describes the field encoding for ISFSR.FTSFSRBit Description Isfsr Update Policy Table F-8D-SFSRBit Description 1 Table F-8D-SFSRBit Description 2 Table F-9defines the encoding of the FT60 field SFSRBit Description 3 MMU Synchronous Fault Status Register FT Fault Type Field Dsfsr Update PolicyFresh fault or miss3 Table F-10DSFSR Update Policy MMU BypassKbytes Table F-11Bypass Attribute Bits on SPARC64 TLB Replacement Policy Automatic TLB Replacement RuleRestriction of sTLB Entry Direct Replacement Page Assembly Language Syntax Please refer to Appendix G of CommonalityPage Software Considerations Please refer to Appendix H of CommonalityPage Extending the Sparc V9 Architecture Please refer to Appendix I of CommonalityPage Changes from Sparc V8 to Sparc Please refer to Appendix K of CommonalityPage Programming with the Memory Models Please refer to Appendix J of CommonalityPage Address Space Identifiers SPARC64 V ASI AssignmentsSPARC64 V ASI Assignments 1 SPARC64 V ASI Assignments 2 TBD Special Memory Access ASIs SPARC64 V ASI Assignments 3 Block Load and Store ASIs Partial Store ASIs Barrier Assist for Parallel Processing Interface DefinitionHigh-Speed Lbsy Read Mechanism ASI Registers High-Speed BST Write MechanismLbsy Control Register ASICLBSYR0, ASICLBSYR1 Bstw Control Register ASICBSTW0, ASICBSTW1 Bstw Busy Status Register Asicbstwbusy Last Barrier Synchronization Status Read ASILBSYR0 Barrier State Write ASIBSTW0, ASIBSTW1EF16 Read Write is ignored Cache Organization Cache Types Table M-1L1I Cache Characteristics Level-1 Instruction Cache L1I Cache Table M-2L1D Cache Characteristics Table M-3L2 Cache CharacteristicsLevel-1 Data Cache L1D Cache Level-2 Unified Cache L2 Cache Cache Coherency Protocols Cache Control/Status InstructionsTable M-4Relationships Between Cache Coherency Protocols Table M-5L2 Cache Moesi States Flush Level-1 Instruction Cache ASIFLUSHL1I 3 L2 Diagnostics Tag Read Level-2 Cache Control Register ASIL2CTRLTable M-6ASIL2CTRL Register Bits 4 L2 Diagnostics Tag Read Registers ASIL2DIAGTAGREADREGPage Interrupt Handling Interrupt Dispatch Membar Interrupt Receive Figure N-2is an example of the interrupt receive flow Interrupt Global Registers Interrupt-Related ASR RegistersInterrupt Vector Dispatch Register Interrupt Vector Dispatch Status Register Reset, REDstate, and errorstate Reset TypesPower-on Reset POR Appendix contains these sections Watchdog Reset WDR Externally Initiated Reset XIRSoftware-Initiated Reset SIR REDstate and errorstate Figure O-1illustrates the processor state transition diagram PA = 000007FFF000000016 Processor State after Reset and in REDstate CPU Fatal Error stateInteger registers Floating Point registers TBA6315 Mask dependent Table O-2ASR State after Reset and in REDstate ASI Register State After Reset and in REDstate 1Counter ASI Register State After Reset and in REDstate 2 Others ASI Register State After Reset and in REDstate 3 Operating Status Register Opsr 11011 Unchanged Hardware Power-On Reset Sequence Firmware Initialization SequenceTo be defined later Page Error Handling Error ClassificationFatal Error Errorstate Transition Error Urgent ErrorInstruction-Obstructing Error Urgent Error Independent of Instruction Execution Restrainable Error Traps for Urgent ErrorsCorrectable Error CE, corrected by hardware Action and Error Control Registers Related to Error HandlingFollowing registers are related to the error handling Table P-1Registers Related to Error Handling Summary of Actions Upon Error Detection Table P-2summarizes what happens when an error is detectedTable P-2Action Upon Detection of an Error 1 Table P-2Action Upon Detection of an Error 2 Ideal specificationDeviation in SPARC64 Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Error Marking for Cacheable Data Format of Error-Marking Data Table P-3Syndrome for Data Marked for ErrorTable P-4Format of Error-Marked Data Table P-6shows the Errormarkid set by the CPU Table P-5ERRORMARKID Bit Description Difference Between Error Marking on SPARC64 IV Table P-7Error Marking on SPARC64 IV and SPARC64 Control of Error Action Asierrorcontrol Value in ASIERRORCONTROL, as defined in Table P-9Table P-8 Asieidr Bit Description Rteue Weaked Ugehandler Fatal Error and errorstate Transition Error Table P-10Format of Asistchgerrorinfo Bit Description4C16 Always 0 Eeother Fatal Error Types Types of errorstate Transition ErrorsCurrent SPARC64 V implementation Urgent Error Ideal specification not implementedTable P-11ASIUGESR Bit Description 1 Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Action of asyncdataerror ADE Trap Conditions that cause ADE trapTable P-11ASIUGESR Bit Description 4 Instend Priv Mugedae Mugeiae Mugeiuge Set the specific register setting Following three sets of registers are updatedFollowing actions are executed in this order State transition Update of ASIUGESR, as shown in Table P-13 Instruction End-Method at ADE TrapUpon completion of a Retry or Done instruction Instend Expected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap Instruction Access Errors Data Access ErrorsSee Appendix F, Memory Management Unit, for details Restrainable Errors Asiasyncfaultstatus Asiafsr DGL1$U2$STLB Ceincomed Uedstbeto UERAWL2$FILLUERAWL2$INSD Implementation Deviation SPARC64 V sets Contents WAY ASIASYNCFAULTADDRU2 register is described in Table P-17 Syndrome Expected Software Handling of Restrainable Errors Contents of PABIT423Page Handling of Internal Register Errors Register Error Handling Excluding ASRs and ASI RegistersTable P-18shows error handling for most registers Terminology used in Table P-18is defined as follows ASR Error Handling Table P-19shows the handling of ASR errorsTable P-19ASR Error Handling ADE trap, W ASI Register Error Handling Error ProtectTerminology used in Table P-20is defined as follows Parity Always Error Detect Condition Error Type Correction Table P-20shows the handling of ASI register errors Table P-20Handling of ASI Register Errors Table P-20Handling of ASI Register Errors Cache Error Handling Handling of a Cache Tag ErrorSPARC64 V Implementation and the Ideal Specification Error in D1 Cache Tag and I1 Cache Tag Error in U2 Unified Level 2 Cache Tag Handling of an I1 Cache Data Error Handling of a D1 Cache Data ErrorCorrectable Error in D1 Cache Data Marked Uncorrectable Error in D1 Cache Data Handling of a U2 Cache Data Error Correctable Error in U2 Cache DataMarked Uncorrectable Error in U2 Cache Data Raw Uncorrectable Error in U2 Cache Data Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache Way Reduction ConditionI1 Cache Way Reduction D1 Cache Way Reduction U2 Cache Way Reduction TLB Error Handling Handling of TLB Entry ErrorsError in TLB Entry Detected on Ldxa Instruction Access Table P-22Error Protection and Detection of TLB Entries Automatic Way Reduction of sTLB Handling of Extended UPA Bus Interface Error Handling of Extended UPA Address Bus ErrorHandling of Extended UPA Data Bus Error STLB Way Reduction Correctable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Performance Instrumentation Performance Monitor OverviewSample Pseudocodes Counter Clear/Set Counter Event Selection and Start Counter Stop and Read Performance Monitor Description Table Q-1Events and Encoding of Performance Monitor Instruction Statistics Events and Encoding of Performance Monitor Instruction Count instructioncounts Counts the committed Floating Multiply-and-Add instructions Trap-Related Statistics MMU Event Counters Counts the occurrences of Tcc instructionsCounts the occurrences of instruction uTLB misses Counts the occurrences of data uTLB misses Cache Event Counters Counts the occurrences of I1 cache missesCounts the occurrences of D1 cache misses Counts the total latency of I1 cache misses Counts the occurrences of L2 cache miss by demand access Counts L2 cache references by demand read access UPA Event Counters Counts the number of Sinvreq packets receivedCounts the number of Scpireq packets received Counts the number of Scpbreq packets received Miscellaneous Counters Barrier-Assist ASI Read Count asirdbarPage UPA Programmer’s Model Mapping of the CPU’s UPA Port Slave AreaTable R-1shows the mapping of the CPU’s UPA port slave area Table R-1CPU’s UPA Port Slave Area Mapping UPA PortID Register Table R-2UPA PortID Register Fields UPA Config Register Table R-3UPA Config Register DescriptionUPA PortID Register Fields Upacap UPA Config Register Description Pcon UPCCAP2MID UpccapPage Summary of Differences between SPARC64 V and UltraSPARC-III SPARC64 V and UltraSPARC-III Differences 1 Table T-1SPARC64 V and UltraSPARC-III Differences 2 UPA Table T-1SPARC64 V and UltraSPARC-III Differences 3 SfsrPage Bibliography General ReferencesPlease refer to Bibliography in Commonality Page Index AugePage ASIINTRW133 Page Error detection action155 DAE DGL1$L2$STLB error194 DGL1$U2$STLB error195 On Jmpl instruction error53 update during MMU trap90 Dmmu ECCerror exception46, 153, 155 Persistence38 Statistics monitoring206-207 FQ17 FSR Immu Update during MMU trap90 Isfsr Lddfa instruction80 PSO41 RMO41 OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB UITLB10, 85, 90 uncorrectable error152 Way reduction194 uDTLB10, 85UnimplementedFPop floating-point trap type70