Completion Stages | Fujitsu Fujitsu SPARC64 V manual

Execution Stages for Cache Access

Memory access requests are passed to the cache access pipeline after the target address is calculated. Cache access stages work the same way as instruction fetch stages, except for the handling of branch prediction. See Section 6.4.1, Instruction Fetch Stages, for details. Stages in instruction fetch and cache access correspond as follows:

Instruction Fetch Stages

Cache Access

IAPs

ITTs

IMMs

IBBs

IRRs

When an exception is signalled, fetch ports and store ports used by memory access instructions are released. The cache access pipeline itself remains working in order to complete outgoing memory accesses. When data is returned, it is then stored to the cache.

6.4.4Completion Stages

■U (Update) — Update of physical (renamed) register.

■W (Write) — Update of architectural registers and retire; exception handling.

■After an out-of-order execution, execution reverts to program order to complete. Exception handling is done in the completion stages. Exceptions occurring in

execution stages are not handled immediately but are signalled when the instruction is completed.1

1. RAS-related exception may be signalled before completion.

34 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

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Fujitsu Fujitsu SPARC64 V manual Completion Stages, Execution Stages for Cache Access

Contents

Sparc JPS1 Release 1.0, 1 July Chapter Page Contents Traps Instructions Sparc JPS1 Implementation-Dependent Traps Memory ModelsImplementation Dependencies Level-1 Instruction Cache L1I Cache Cache Organization 125 Cache Types Reset, REDstate, and errorstate 137 Reset Types Error Handling 149 Error ClassificationFatal Error Asistchgerrorinfo UPA Programmer’s Model General ReferencesIndex Page Overview Navigating the SPARC64 V Implementation SupplementFonts and Notational Conventions Microarchitecture for High Performance SPARC64 V processorHigh Integration High Reliability and High Integrity Advanced RAS features for caches Advanced RAS features for the coreExtended RAS interface to software Component Overview Asynchronous data error ADE trap for additional errors SX-Unit Execution Unit EU Instruction Control Unit IU1Instruction Control Unit Major Blocks 2Execution Unit Major Blocks Storage Unit Major Blocks Storage Unit SU 4Secondary Cache and External Access Unit Major Blocks Secondary Cache and External Access Unit SXU Instruction dispatch Synonym instruction initiation Definitions Issue-stalling Sync Synonym machine sync Page Architectural Overview Page Please refer to , Data Formats in Commonality Data FormatsPage Nonprivileged Registers Registers FSRnonstandardfp NS Floating-Point State Register FSRFSRversion ver FSRfloating-pointtraptype ftt Tick Tick Register Privileged RegistersTrap State Tstate Register FSR Conformance Ancillary State Registers ASRs Version VER RegisterPerformance Control Register PCR ASR 1shows the values for the VER register for SPARC64 Ovro OVF Registers Referenced Through ASIs Accessibility as described above impl. dep. #250Performance Instrumentation Counter PIC Register ASR Dispatch Control Register DCR ASR VM70 PM70 IU Deferred-Trap Queue Floating-Point Deferred-Trap Queue FQData Watchpoint Registers Instruction Trap Register Instructions Instruction ExecutionData Prefetch Instruction Prefetch 1SPARC64 V Syncing Instructions Syncing Instructions Instruction Formats and Fields 2Instruction Fields Specific to SPARC64Yes Control-Transfer Instructions CTIs Instruction CategoriesCall and Jmpl Instructions Control transfer CTI Implementation-Dependent Instructions Floating-Point Operate FPop Instructions Instruction Fetch Stages Processor Pipeline Brhis Execution Stages Issue Stages Completion Stages Execution Stages for Cache Access Traps Processor States, Normal and Special TrapsPlease refer to .1 of Commonality REDstate ErrorstateREDstate Trap Table REDstate Execution Environment Trap Categories Reset TrapsDeferred Traps Uses of the Trap Categories Trap-Table Entry Addresses Trap ControlPIL Control Trap Type TT Exception and Interrupt Descriptions Trap ProcessingDetails of Supported Traps Sparc JPS1 Implementation-Dependent TrapsPage Sparc V9 Memory Model on Memory Models Overview Mode ControlSparc V9 Memory Model Synchronizing Instruction and Data Memory Release 1.0, 1 July Memory Models Page Table A-1Implementation-Specific Instructions Instruction Definitions SPARC64 V ExtensionsPage Block Load and Store Instructions VIS Invalid Valid Implementation-Dependent Instructions Call and Link Format Floating-Point Multiply-Add/SubtractPage Non-Trapping cexc When FSR.NS = Non-Trapping aexc When FSR.NS =Operation, and inexact, respectively Jump and Link Exceptions fpdisabled Format 3 Ldda Load Quadword, Atomic Physical Memory Barrier Bits in the cmask Field Order Constraints Imposed by mmask Bits Partial Store VIS Prefetch Data01816 Read State Register Table A-7describes prefetch variants implemented in SPARC64Table A-7Prefetch Variants Write State Register Deprecated InstructionsStore Barrier Page Floating-Point Nonstandard Mode Ieee Std 754-1985 Requirements forTraps Inhibiting Results Fpexceptionother Exception ftt=unfinishedFPop Denormalized number, eres is less than zero Generates an unfinishedFPop exceptionUnfinishedFPop Boundary Conditions Table B-2unfinishedFPop Boundary Conditions Pessimistic Zero Pessimistic Overflow Operation Under FSR.NS =Table B-3Conditions for a Pessimistic Zero Table B-4Pessimistic Overflow Conditions UnfinishedFPop4 Floating-Point Exceptional Conditions and Results Yes and op2 Nv, dNaN Nonarithmetic Operations Under FSR.NS =Page Implementation Dependencies Definition of an Implementation DependencyPlease refer to Section C.1 of Commonality Implementation Dependency Categories Hardware CharacteristicsList of Implementation Dependencies Please refer to Section C.2 of Commonality Table C-1SPARC64 V Implementation Dependencies Entering errorstate on implementation-dependent errors Reset trapErrorstate processor state Deferred traps Clean windows trap Data access FPU trapFlush instruction Floating-point underflow detection MMU disabled prefetch behavior SIRenable control flagIMPDEPn instructions Unimplemented LDD trap Unimplemented values for PSTATE.MM Implicit ASI when TLCoherence and atomicity of memory operations Implementation-dependent memory model Table C-1SPARC64 V Implementation Dependencies 7 Table C-1SPARC64 V Implementation Dependencies 8 Table C-1SPARC64 V Implementation Dependencies 9 Table C-1SPARC64 V Implementation Dependencies 10 256 255257 258 Please refer to Appendix D of Commonality Formal Specification of the Memory ModelsPage Instruction65 Opcode MapsPage Virtual Address Translation Memory Management Unit Table F-1Organization of SPARC64 V TLBs Translation Table Entry TTE Release 1.0, 1 July Chapter F Memory Management Unit TSB Organization TSB Pointer FormationTSB Pointer Formation TLB miss 64 16-67 Faults and Traps Instructionaccessexception Reset, Disable, and REDstate Behavior Access Modes Supervisor read/write Accessing MMU RegistersInternal Registers and ASI operations Asimcntl Memory Control Register Table F-3MCNTL Field Description 10.4 I/D TLB Data In, Data Access, and Tag Read RegistersRMD JPS1TSBPPage TLB# Table F-4MMU TLB Data Access Address Assignment Kbyte page entry MMU TLB Tag Access Register MMU I/D Synchronous Fault Status Registers I-SFSR, D-SFSR 10.9 I/D Synchronous Fault Status Registers I-SFSR, D-SFSR10.7 I/D TSB Extension Registers TSB Base Registers EID Table F-5I-SFSRBit Description FT60 Error Description Table F-6describes the field encoding for ISFSR.FTSFSRBit Description Table F-8D-SFSRBit Description 1 Isfsr Update Policy Table F-8D-SFSRBit Description 2 SFSRBit Description 3 Table F-9defines the encoding of the FT60 field MMU Synchronous Fault Status Register FT Fault Type Field Dsfsr Update PolicyFresh fault or miss3 MMU Bypass Table F-10DSFSR Update PolicyKbytes Table F-11Bypass Attribute Bits on SPARC64 TLB Replacement Policy Automatic TLB Replacement RuleRestriction of sTLB Entry Direct Replacement Page Please refer to Appendix G of Commonality Assembly Language SyntaxPage Please refer to Appendix H of Commonality Software ConsiderationsPage Please refer to Appendix I of Commonality Extending the Sparc V9 ArchitecturePage Please refer to Appendix K of Commonality Changes from Sparc V8 to SparcPage Please refer to Appendix J of Commonality Programming with the Memory ModelsPage Address Space Identifiers SPARC64 V ASI AssignmentsSPARC64 V ASI Assignments 1 TBD SPARC64 V ASI Assignments 2 SPARC64 V ASI Assignments 3 Special Memory Access ASIs Partial Store ASIs Block Load and Store ASIs Barrier Assist for Parallel Processing Interface DefinitionHigh-Speed Lbsy Read Mechanism ASI Registers High-Speed BST Write MechanismLbsy Control Register ASICLBSYR0, ASICLBSYR1 Bstw Busy Status Register Asicbstwbusy Bstw Control Register ASICBSTW0, ASICBSTW1 Barrier State Write ASIBSTW0, ASIBSTW1 Last Barrier Synchronization Status Read ASILBSYR0EF16 Read Write is ignored Cache Types Cache Organization Level-1 Instruction Cache L1I Cache Table M-1L1I Cache Characteristics Table M-3L2 Cache Characteristics Table M-2L1D Cache CharacteristicsLevel-1 Data Cache L1D Cache Level-2 Unified Cache L2 Cache Cache Control/Status Instructions Cache Coherency ProtocolsTable M-4Relationships Between Cache Coherency Protocols Table M-5L2 Cache Moesi States ASIFLUSHL1I Flush Level-1 Instruction Cache 3 L2 Diagnostics Tag Read Level-2 Cache Control Register ASIL2CTRLTable M-6ASIL2CTRL Register Bits ASIL2DIAGTAGREADREG 4 L2 Diagnostics Tag Read RegistersPage Interrupt Dispatch Interrupt Handling Membar Figure N-2is an example of the interrupt receive flow Interrupt Receive Interrupt-Related ASR Registers Interrupt Global RegistersInterrupt Vector Dispatch Register Interrupt Vector Dispatch Status Register Reset Types Reset, REDstate, and errorstatePower-on Reset POR Appendix contains these sections Watchdog Reset WDR Externally Initiated Reset XIRSoftware-Initiated Reset SIR Figure O-1illustrates the processor state transition diagram REDstate and errorstate PA = 000007FFF000000016 CPU Fatal Error state Processor State after Reset and in REDstateInteger registers Floating Point registers Mask dependent TBA6315 Table O-2ASR State after Reset and in REDstate ASI Register State After Reset and in REDstate 1Counter Others ASI Register State After Reset and in REDstate 2 ASI Register State After Reset and in REDstate 3 11011 Unchanged Operating Status Register Opsr Hardware Power-On Reset Sequence Firmware Initialization SequenceTo be defined later Page Error Handling Error ClassificationFatal Error Errorstate Transition Error Urgent ErrorInstruction-Obstructing Error Urgent Error Independent of Instruction Execution Restrainable Error Traps for Urgent ErrorsCorrectable Error CE, corrected by hardware Registers Related to Error Handling Action and Error ControlFollowing registers are related to the error handling Table P-1Registers Related to Error Handling Summary of Actions Upon Error Detection Table P-2summarizes what happens when an error is detectedTable P-2Action Upon Detection of an Error 1 Table P-2Action Upon Detection of an Error 2 Ideal specificationDeviation in SPARC64 Table P-2Action Upon Detection of an Error Error Marking for Cacheable Data Error Marking for Cacheable Data Error Format of Error-Marking Data Table P-3Syndrome for Data Marked for ErrorTable P-4Format of Error-Marked Data Table P-5ERRORMARKID Bit Description Table P-6shows the Errormarkid set by the CPU Table P-7Error Marking on SPARC64 IV and SPARC64 Difference Between Error Marking on SPARC64 IV Value in ASIERRORCONTROL, as defined in Table P-9 Control of Error Action AsierrorcontrolTable P-8 Asieidr Bit Description Rteue Ugehandler Weaked Table P-10Format of Asistchgerrorinfo Bit Description Fatal Error and errorstate Transition Error4C16 Always 0 Eeother Fatal Error Types Types of errorstate Transition ErrorsCurrent SPARC64 V implementation Urgent Error Ideal specification not implementedTable P-11ASIUGESR Bit Description 1 Table P-11ASIUGESR Bit Description 2 Table P-11ASIUGESR Bit Description 3 Conditions that cause ADE trap Action of asyncdataerror ADE TrapTable P-11ASIUGESR Bit Description 4 Instend Priv Mugedae Mugeiae Mugeiuge Following three sets of registers are updated Set the specific register settingFollowing actions are executed in this order State transition Instruction End-Method at ADE Trap Update of ASIUGESR, as shown in Table P-13Upon completion of a Retry or Done instruction Instend Expected Software Handling of ADE Trap Void ExpectedsoftwarehandlingofADEtrap Instruction Access Errors Data Access ErrorsSee Appendix F, Memory Management Unit, for details Asiasyncfaultstatus Asiafsr Restrainable Errors Ceincomed DGL1$U2$STLB UERAWL2$FILL UedstbetoUERAWL2$INSD Implementation Deviation SPARC64 V sets WAY Contents Syndrome ASIASYNCFAULTADDRU2 register is described in Table P-17 Contents of PABIT423 Expected Software Handling of Restrainable ErrorsPage Register Error Handling Excluding ASRs and ASI Registers Handling of Internal Register ErrorsTable P-18shows error handling for most registers Terminology used in Table P-18is defined as follows Table P-19shows the handling of ASR errors ASR Error HandlingTable P-19ASR Error Handling ADE trap, W Error Protect ASI Register Error HandlingTerminology used in Table P-20is defined as follows Parity Always Error Detect Condition Correction Error Type Table P-20Handling of ASI Register Errors Table P-20shows the handling of ASI register errors Table P-20Handling of ASI Register Errors Handling of a Cache Tag Error Cache Error HandlingSPARC64 V Implementation and the Ideal Specification Error in D1 Cache Tag and I1 Cache Tag Error in U2 Unified Level 2 Cache Tag Handling of an I1 Cache Data Error Handling of a D1 Cache Data ErrorCorrectable Error in D1 Cache Data Marked Uncorrectable Error in D1 Cache Data Correctable Error in U2 Cache Data Handling of a U2 Cache Data ErrorMarked Uncorrectable Error in U2 Cache Data Raw Uncorrectable Error in U2 Cache Data Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache Way Reduction ConditionI1 Cache Way Reduction U2 Cache Way Reduction D1 Cache Way Reduction Handling of TLB Entry Errors TLB Error HandlingError in TLB Entry Detected on Ldxa Instruction Access Table P-22Error Protection and Detection of TLB Entries Automatic Way Reduction of sTLB Handling of Extended UPA Address Bus Error Handling of Extended UPA Bus Interface ErrorHandling of Extended UPA Data Bus Error STLB Way Reduction Correctable Error on Extended UPA Data Bus UE in Outgoing Data to Extended UPA Data Bus Page Performance Monitor Overview Performance InstrumentationSample Pseudocodes Counter Clear/Set Counter Stop and Read Counter Event Selection and Start Table Q-1Events and Encoding of Performance Monitor Performance Monitor Description Events and Encoding of Performance Monitor Instruction Statistics Counts the committed Floating Multiply-and-Add instructions Instruction Count instructioncounts Trap-Related Statistics Counts the occurrences of Tcc instructions MMU Event CountersCounts the occurrences of instruction uTLB misses Counts the occurrences of data uTLB misses Counts the occurrences of I1 cache misses Cache Event CountersCounts the occurrences of D1 cache misses Counts the total latency of I1 cache misses Counts L2 cache references by demand read access Counts the occurrences of L2 cache miss by demand access Counts the number of Sinvreq packets received UPA Event CountersCounts the number of Scpireq packets received Counts the number of Scpbreq packets received Barrier-Assist ASI Read Count asirdbar Miscellaneous CountersPage Mapping of the CPU’s UPA Port Slave Area UPA Programmer’s ModelTable R-1shows the mapping of the CPU’s UPA port slave area Table R-1CPU’s UPA Port Slave Area Mapping Table R-2UPA PortID Register Fields UPA PortID Register Table R-3UPA Config Register Description UPA Config RegisterUPA PortID Register Fields Upacap UPA Config Register Description UPCCAP2 PconMID UpccapPage SPARC64 V and UltraSPARC-III Differences 1 Summary of Differences between SPARC64 V and UltraSPARC-III UPA Table T-1SPARC64 V and UltraSPARC-III Differences 2 Sfsr Table T-1SPARC64 V and UltraSPARC-III Differences 3Page Bibliography General ReferencesPlease refer to Bibliography in Commonality Page Auge IndexPage ASIINTRW133 Page DAE Error detection action155 DGL1$L2$STLB error194 DGL1$U2$STLB error195 Dmmu On Jmpl instruction error53 update during MMU trap90 Persistence38 ECCerror exception46, 153, 155 Statistics monitoring206-207 FSR FQ17 Immu Isfsr Update during MMU trap90 PSO41 RMO41 Lddfa instruction80 OBP Release 1.0, 1 July Chapter Index PTE Release 1.0, 1 July Chapter Index Page TLB UITLB10, 85, 90 uncorrectable error152 Way reduction194 uDTLB10, 85UnimplementedFPop floating-point trap type70