Fujitsu Fujitsu SPARC64 V manual Error Detect Condition

(2 of 3)

Column Term Meaning

Error Detect Condition

Always	Error is always checked.
AUG always	Error is checked when (ASI_ERROR_CONTROL.UGE_HANDLER = 0) &&
	(ASI_ERROR_CONTROL.WEAK_ED = 0).
LDXA	Error is checked when the register is read by LDXA instruction.
LDXA #I	Error is checked when the register is read by LDXA instruction.
	Also, the register is used for the calculation of IMMU_TSB_8KB_PTR and
	IMMU_TSB_64KB_PTR. When the register has a UE and the register is used
	for the calculation of ASI_IMMU_TSB_PTR registers, the UE is propagated to
	the ASI_IMMU_TSB_PTR registers. Upon execution of the LDXA instruction
	to read ASI_IMMU_TSB_PTR with the propagated UE, the IUG_TSBP error is
	detected.
LDXA #D	Error is checked when the register is read by LDXA instruction.
	Also, the register is used for the calculation of DMMU_TSB_8KB_PTR,
	DMMU_TSB_64KB_PTR, and DMMU_TSB_DIRECT_PTR. When the register has
	a UE and the register is used for the calculation of ASI_DMMU_TSB_PTR
	registers, the UE is propagated to the ASI_DMMU_TSB_PTR registers. Upon
	execution of the LDXA instruction to read ASI_DMMU_TSB_PTR with the
	propagated UE, the IUG_TSBP error is detected.
ITLB write	Error is checked at the ITLB update timing after completion of the STXA
	instruction to write or demap an ITLB entry.
DTLB write	Error is checked at the DTLB update timing after the completion of the STXA
	instruction to write or demap a DTLB entry.
Use for TLB	Error is checked when the register is used for a TLB reference.
Enabled	Error is checked when the facility is enabled.

intr_receive Error is checked when the UPA interrupt packet is received. When an uncorrectable error is detected in the received interrupt packet, the vector interrupt trap is caused but ASI_INTR_RECEIVE.BUSY = 0 is set. In this case, a new interrupt packet can be received after software writes ASI_INTR_RECEIVE.BUSY = 0.

BV interface	Uncorrected error in the Barrier Variable transfer interface between the
	processor and the memory system is checked during the AUG_always
	period.

184 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002