Fujitsu Fujitsu SPARC64 V manual Expected Software Handling of ADE Trap

TABLE P-14defines each instruction end-method after an ADE trap.

TABLE P-14Instruction End-Method After async_data_error Exception

	Precise	Retryable But Not Precise	Not Retryable
Instructions executed after	Ended (Committed).
the last ADE, IAE, or DAE	The instructions without UGE complete as defined in the architecture. The
trap and before the trapped	instruction with UGE was unpredictable value to its output (destination register or,
instruction referenced by	in the case of a store instruction, destination memory location).
TPC.
The trapped instruction	Not executed.	The output of the instruction is	The output of the instruction is
referenced by TPC		incomplete.	incomplete.
		Part of the output may be	Part of the output may be
		changed, or the invalid value	changed, or the invalid value
		may be written to the instruction	may be written to the instruction
		output. However, the	output. However, the
		modification to the invalid target	modification to the invalid target
		that is not defined as instruction	that is not defined as instruction
		output is not executed.	output is not executed.
		The following modifications are	A store to an invalid address is
		not executed:	not executed. (Store to a valid
		• Store to the cacheable area	address with uncorrected data
		including cache.	may be executed.)
		• Store to the noncacheable area.
		• Output to the source register of
		the instruction (destructive
		overlap)
Instructions to be executed	Not executed.	Not executed.	Not executed.
after the instruction
referenced by TPC
The possibility of resuming	Possible.	Possible.	Impossible.
the trapped program by
executing the RETRY
instruction to the %tpc
when the trapped program
is not damaged at the
single-ADEtrap

P.4.4 Expected Software Handling of ADE Trap

The expected software handling of an ADE trap is described by the pseudo C code below. The main purpose of this flow is to recover from the following errors as much as possible:

■An error in the CPU internal RAM or register file

■An error in the accumulator

■An error in the CPU internal temporary registers and data bus

Release 1.0, 1 July 2002 F. Chapter P Error Handling 171