Fujitsu Fujitsu SPARC64 V manual Weaked, Ugehandler

TABLE P-9ASI_ERROR_CONTROL Bit Description (Continued)

Bit	Name	RW	Description
1	WEAK_ED	RW	Weak Error Detection. Controls whether the detection of I_UGE and DAE is
			suppressed:
			When WEAK_ED = 0, error detection is not suppressed.
			When WEAK_ED = 1, error detection is suppressed if the CPU can continue
			processing.
			When I_UGE or DAE is detected during instruction execution while
			WEAK_ED = 1, the value of the output register or the store target memory
			location become unpredictable.
			Even if WEAK_ED = 1, I_UGE or DAE is detected and corresponding trap is
			caused when the CPU cannot continue processing by ignoring the error.
			WEAK_ED is the trap disabling mask for A_UGE and restrainable errors, as
			defined in TABLE P-2.
			When a multiple-ADEtrap is caused (I_UGE, IAE, or DAE detection while
			ASI_ERROR_CONTROL.UGE_HANDLER = 1), WEAK_ED is set to 1 by hardware.
0	UGE_HANDLER	RW	Designates whether hardware can expect a UGE handler to run in privileged
			software (operating system) when a UGE error occurs:
			0: Hardware recognizes that the privileged software UGE handler does not
			run.
			1: Hardware expects that the privileged software UGE handler runs.
			UGE_HANDLER is the trap disabling mask for A_UGE and restrainable errors,
			as defined in TABLE P-2.
			The value of UGE_HANDLER determines whether a multiple-ADEtrap is
			caused or not upon detection of I_UGE, IAE, and DAE.
			When an async_data_error trap occurs, UGE_HANDLER is set to 1.
			When a RETRY or DONE instruction is completed, UGE_HANDLER is set to 0.
Other	Reserved	R	Always reads as 0.

162 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002