Fujitsu Fujitsu SPARC64 V manual Operation Under FSR.NS =, Pessimistic Overflow

TABLE B-5

TABLE B-3Conditions for a Pessimistic Zero

			Conditions
Operations	One operand is denormalized1		Both are denormalized	Both are normal fp-number2
FdTOs	always		—	eres ≤ -25
FMULs,	single precision: Er ≤ −	25	Always	single precision: eres ≤ −	25
FMULd	double precision: Er ≤ −	54		double precision: eres ≤ −	54
FDIVs,	single precision: Er ≤ −	25	Never	single precision: eres ≤ −	25
FDIVd	double precision: Er ≤ −	54		double precision: eres ≤ −	54

1.Both operands are non-zero, non-NaN, and non-infinity numbers.

2.Both may be zero, but both are non-NaN and non-infinity numbers.

Pessimistic Overflow

If a condition in TABLE B-4is true, SPARC64 V regards the operation as having an overflow condition.

TABLE B-4Pessimistic Overflow Conditions

Operations	Conditions
FDIVs	The divisor (operand2; rs2) is a denormalized number and, Er ≥	255.
FDIVd	The divisor (operand2; rs2) is a denormalized number and, E ≥	2047.

B.6.2 Operation Under FSR.NS = 1

When FSR.NS = 1 (nonstandard mode), SPARC64 V zeroes all the input denormalized operands before the operation and signals an inexact exception if enabled. If the operation generates a denormalized result, SPARC64 V zeroes the result and also signals an inexact exception if enabled. The following list defines the operation in detail.

■If either operand is a denormalized number and both operands are non-zero, non- NaN, and non-infinity numbers, the input denormalized operand is replaced with a zero with same sign, and the operation is performed. If enabled, inexact

exception is signalled; an fp_exception_ieee_754 (tt = 02116) is generated, with nxc=1 in FSR.cexc (FSR.ftt=0116; IEEE754_exception). However, if the operation is FDIV(s,d) and either a division_by_zero or an invalid_operation condition is detected, or if the operation is FSQRT(s,d) and an invalid_operation condition is detected, the inexact condition is not reported.

■If the result before rounding is a denormalized number, the result is flushed to a zero with a same sign and signals either an underflow exception or an inexact exception, depending on FSR.TEM.

As observed from the preceding, when FSR.NS = 1, SPARC64 V generates neither an unfinished_FPop exception nor a denormalized number as a result.

Release 1.0, 1 July 2002 F. Chapter B IEEE Std 754-1985 Requirements for SPARC V9 65