Theory of Operation
3-46 2715 Spectrum Analyzer Service Manual
TEXT3. This bit, w hen high, places page three of the four poss ible readout pages
on the CRT.Any number of text pages may be displayed on the CRT, however
the resulting display may not be readable,and will flicker severely.
TEXT2. This bit, when high, pl acesp aget wo oft hefo urp ossible readout pages
on the CRT.Any number of text pages may be displayed on the CRT, however
the resulting display may not be readable,and will flicker severely.
TEXT1. This bit, when high, pl acesp ageo ne(readouts) of the four possible
readout pages on the CRT.Any number of text pages may be displayed on the
CRT,however the resulting display may not be readable, and will flicker
severely.
DISPD. This bit, when high, enables the display of WaveformD on the CRT.
DISPC. This bit, when high, enables the displayof Waveform C on the CRT.
DISPB. This bit, when high, enables the displayof Waveform B on the CRT.
DISPA. This bit, when high, enablesthe display of Waveform A on the CRT.
Scroll Register. The Scroll Register is located atI/O memory location 0x0FA03.
The Scroll Register is write only register.Reading from this register will return
the vertical data currentlystored in the Maximum S torageregister. This value
may be either a maximum peak, if the acquisition mode is Max Peak, or sample,
if the acquisition mode is Sample. Afterreading this register, it is cleared.
Table3 - 10: Scroll Register
Bit
Number Mnemonic
Activity
Level Description
7MCREG2 High Enables Mode Control Register 2
6Not used —
5Not used —
4Not used —
3SCRL3 High Readout Scroll bit 3
2SCRL2 High Readout Scroll bit 3
1SCRL1 High Readout Scroll bit 3
0SCRL0 High Readout Scroll bit 3
MCREG2. This bit, when low, holds Mode Control Register 2 in the cleared
(disabled) state. Setting the MCREG2 bit high will allow successful writes to
Mode Control Register 2.
SCRL[0..3]. These four bits determine how far up the screen the bottom row of
text should be displayed, anywhere from0 to 15 lines.