Theory of Operation
2715 Spectrum Analyzer Service Manual 3-47
Marker Position Registers. There are two Marker Position Registers. One register
for Marker 1 and a second registerfor Marker 2. Marker Position Register 1 uses
I/O port locations 0x0FC00 through 0x0FDFF. MarkerPosition Register 2 uses
I/O port locations 0x0FE00 through 0x0FFFF.Each port locationcorresponds to
a horizontal position on the screen.B y writingany data to one of the I/O ports
inside the above range, the corresponding markerwill be placed at the hori zontal
position, on the CRT, representedby the lower nine bits of the port address.
For example, writing 0x55 to I/O address 0x0FCE3 will placeMarker 1 at
horizontal screen position 0x0E3 (227),while writing 0xA1 to I/O address
0x0FFF9 will placeMarker 2 at horizontalscreen position 0x1F9 (505).
The Display Storage board is best describedby breaking it up into several
sections. These sections include Address Bufferingand Decoding, the Control
Registers, the Horizontal Input and TrackingA/D, the Vertical Input, the Vertical
Data Processor and NVRAM, the Readouts and WaveformDrawing, the
Horizontal Output, the Vertical Output, and the MiscellaneousDecoupling. The
following sections will des cribe each one of these in detail.
Address Buffering and Decoding. The Address Buffering and Decoding section
consists of a 74HCT245 bidirectional bus transceiver (U22), and a GAL20V8
PAL (U29).The purpose of this section is to decode the incoming address lines
into the various enable signals requiredby the Display Storage board, buffer the
data lines from the CPU Board, and buffer the BCLK signal for distribution
around the board.
U22, the bus transceiver,is used to allow data on or off the Display Storage
board. This bus transceiver can only be enabled afterthe RAM arbitrator grants
access to a request from the Micropro cessor.
The PAL, U29, decodes the addresslines B A19 through BA9, to generate the
request signal UPREQ, and the enablesignals PORTVEC, MKR1_LT, and
MKR2_LT.In addition the signals RDEN and WREN are generated on read or
writes to or from the board. Thememory map (Table 3--11)shows which signals
are generated from which address ranges. A descrip tion of each signal from U29
is given below.
UPREQ. This signal becomes active (high) any time the board is accessed by the
CPU. The UPREQ sign al is fed into the RAM arbitrator to request access to the
board.
PORTVEC. This signal becomes acti ve (high) at any access to the Control
registers (I/O port addresses0xFA00 through 0xFBFF). This signal also causes
the UPREQ signal to become active.
MKR1_LT. This signal becomes active (high) at any access to the Marker 1 po rt
addresses (I/O port addresses0xFC00 through 0xFDFF ). This signalalso causes
the UPREQ signal to become active.
Circuit Description