Theory of Operation
3-30 2715 Spectrum Analyzer Service Manual
FSTROBE
FM
Main
Main
DAC
SWP
DAC
DIG
1stLO Beat to
Counterfor Lock
Verification
PhaseG ate
HarmGen
VCO Module
(StrobeGen)
Summing
andF ixed
Scaling
VREF
1stLO
1stLO to 1st Converter
N-F Strobe
PLL
DAC
VREF
DIG
Microprocessor
SerialO ut
SerialIn
FM
DAC
DIG
MainCoil
Driver
Summing
andF ixed
Scaling
DIG
1stLO
VREF
DIG Decade
Atten
AnalogSweep In
LockLimits
Comparator
ErrorAmp &
LoopF ilter
Phase
Error
Voltage
Figure 3- 14: Phase Lock Center Frequency Control Configuration for Narrow Spans (Locked, Sweep VCO)
The FM coil is driven with the output of the phase lock error amplifier, U713,
only.
The VCO is active continuously and is tuned by a fixedbias summed with
VCFCU from DAC U950B, VCFC L from DAC U850A (routed through
U757D), and sweep voltage VSWP PLL (routed through U757B).
The PLCFC board has four 12 bit DACs in two IC packages, U850 and U950.
On the digital side, each p ackage has four data lines, three address lines , and two
control lines. The DACs contain internal registersfor the 12 bit words associated
with each analog output and, therefo re, the microprocessor must write multiple
4 bit words to a package in orderto set up a new output.
These are multiplying DACs. Each deliversan output current that is the product
of an analog voltage (calledthe reference) and the 12 bit digital word. These
units can correctly dealwith either polarity of reference voltage. Three of them
(U850A, U950A, and U950B) are supplied fixed referencevoltages and serve
simply as computer controlled DC sources .
DAC U850A is called the FM DAC but serves two roles. In non phaselocked
spans, its output ultimately ends up fine tuning the 1st LO centerfrequency
through the FM coil.
Digital to AnalogConversion