Tektronix 2715 Summary of Digital Control Lines on Phase Lock Center Frequency Control Module

Theory of Operation
3-32 2715 Spectrum Analyzer Service Manual
This is the loop back path referred to earlier for checkin g the interface. This
register may also be loadedwith up to eight bits of parallel data for subsequent
serial transferto the microprocessor. Only three bits are used. Bits 7 and 8 are the
signals (INCR MAIN and DCR MAIN) from the lock limits comparator,and bit
5 is wired to logic 1 as a board identity.
The gating of CLKI-- and CLKO into the output shift register (by CFCACK--
and LOADEXM, respectively) is partlya matter of source selection and is also
necessary because both clock signals are used b y other boards in the system at
some times.
Any transition on either INCR MAIN or DCR MAIN (or both) will load the new
states of those lines into the output shift register. (The various sections of U360
serve as edge detectorsto generate the load command to the shift register.)
Further, if LKINTENis high at the time, U471B will end up SET, interrupting
the microprocessor by way of CFCREQ--. The line READEXM provides a direct
method of setting the interrupt, if desired.Any transition on LKINTEN will also
cause the shift register to be loaded, prov iding a forced means for checking the
status of the lock lines at any time. Themicroprocessor uses CFCACK-- to clear
U471 of the interrupt (in addition to thegating function mentioned above).
READEXM. Low to high transition forces CFC interrupt.
LOADEXM. High level gates CLKO into output shift register clockinput.
DEGAUSS. High level forces 1st LO main coil currentto zero.
CNTSELA and CNTS ELB. These signals are decoded to set s tate of selector
switch in VCO module. Both high is strobe OFF. CNTSELA high and
CNTSELB low is count VCO. CNTSELA low and CNTSELB high is count beat
frequency.Both low is strobe ON but no count selected.
PLLCON. High level commands phase lock configuration.
LKINTEN. High level enables interrupton transition of either lock limit
comparator line.
CAPCON. High level connects noise reduction capacitoracross 1st LO main
coil.
SWDECA. A and B are decoded to select settingof sweep decade attenu ator.
Both low is straight through. A high and B low is divide by 10. A low and B
high is divide by 100. Both high is disconnect sweep.
SWSELA. A and B are decoded in U274 to operateswitches that direct sweep
waveform to proper destination.
SWSELB. Both low is sweep main coil. A high and B low is sweep FM coil. A
low and B high is sweep VCO. Both high is no sweep.
Summary of Digital
Control Lines on Phase
Lock Center Frequency
Control Module