Theory of Operation
2715 Spectrum Analyzer Service Manual 3-59
The Error Amplifier comparesthe current state of the Integrator Circuity output
and the current input voltagefrom the DAC and generates an error voltage. This
error voltage is then fedinto a high current buffer made up of Q4, Q5, and CR7.
CR7 and R179 are used to insure that transistorQ4 is properly biased. The high
current bufferis required to ensure that the capacitor in the Sample and Hold
section is chargedquickly. The Sample and Hold circuit basically samples the
error voltage by closing theanalog switch, U34, for 400 ns, charging capacitor
C94. When the switch opens the value of the error voltage should be across the
capacitor.The operational amplifier U57 then buffers and amplifies the error
voltage such that when it is applied to theIntegrator sexton ramp the correct
slope is produced. The potentiometer,R181, Vector Length, is used toadjust the
slope of the output ramp to match the waveform data drawing rate. The input of
the Integrator sectionconsists of two resistors with a capacitor to ground
between them. This RC network, along with the resistor in serieswith the
integrating capacitor, C93, form a netwo rk that prevents an early step when
integrating over a long distance.The step is caused by the rapid change in error
voltage coupling straight through the integrating capacitor.The resistors R112
and R183 along with capacitor C93 and operationalamplifier U57 form the
Integration Section of the Integrator.The output of the Integrator is then fed
through a DC641 analog switch and into the output buffer,U35, of the Vertical
Output Section. Finally a potentiometer,R174, Vector Offset, is providedto
compensate for the injectioncharge of the DC641 into the hold capacitor, C94.
The signal for drawing the Readouts is taken directly offU4, the DAC current to
voltage buffer,and fed through an analog switch into the output buffer. Thegain
variations between the waveformand readout is accomplished by s lightly
increasing the gain of the Integrator,such that the Readouts will always remain
inside the graticule. In order to ensure that the Readouts will always appear
centered inside the graticule,the waveform is forced slightly lower by adjusting
the Vertical Offset to +40 mV.Then wh en the waveform display is centered on
the screen using the Vertical Output Offsetpotentiometer everything aligns
correctly.
The final bufferin the Vertical Output Section provides both gain and offset
adjustments, VerticalOutput Gain (VOG), R42, and Vertical Output Offset
(VOO), R63. The two analog switches which drive the DSVER signal are used
to switch between the LOGVID signal, forreal time analog display, and the
VERT signal fordigitized display (readouts).
MiscellaneousDecoupling. C ontainedon the Miscellaneous Decoupling page of
the schematics are all of the decoup ling capacitors. There is one 0.1 F capacito r
for each digital integrated circuit on the bo ard. Also shown on this page are
several 221 Ωresistors. These resistors are required to resto re the power
dissipation to a minimum level to ensure thatthe power supply can maintain its
supply voltages well centered.
Power Up Reset. The power up reset circuit is included to ensurethat a valid reset
signal is generated when theinstrument is turned on.