4-1010 July 1998
Notes
1 Per Analog Devices AD1890 data sheet, where applicable.
2 With 6.144 MHz MCLK/2 input.
3 20 Hz to 20 kHz, full-scale input, through sample rate converter, to output via passthrough.
4 From input, through sample rate converter, to output via passthrough.
5 When installed in ISP-100.
6 When installed in ISP-100.
7 Input samples longer than 20 bits are truncated to 20 bits.
8 Least four significant bits are zero filled.
9 DC to 20 kHz input, through sample rate converter, to output via passthrough.
10 20 Hz to 20 kHz, -60 dB input, through sample rate converter, to output via passthrough.
11 From input, through sample rate converter, to output via passthrough.
12 From SDO0 pin on card connector, through transmitter, to output. The fractional-sample delay is inherent in the Crystal CS8404 transmitter.
13 From input, through sample rate converter, to output via passthrough.
14 Frequency is tripled by a PLL on the MDM-1 before being applied to the sample rate converter.
15 Must be derived from MCLK+.
16 Must be derived from MCLK+.
17 Must be derived from MCLK+.
18 Must be derived from MCLK+.
19 Must be nominally 48 kHz when installed in ISP-100.
20 From input to output via passthrough.
21 From input to output via passthrough.
22 When installed in ISP-100.
23 DC to Fs/2.
24 From input to output via passthrough.
25 From input to output via passthrough.
26 From input, through receiver, to SDI0 pin on card connector.
27 From SDO0 pin on card connector, through transmitter, to output. The fractional-sample delay is inherent in the Crystal CS8404 transmitter.
28 From input to output via passthrough.
29 Must be Fs x 256.
30 Must be derived from MCLK+.
31 Must be derived from MCLK+.
32 Must be derived from MCLK+.
33 Must be derived from MCLK+.