5.
6.
7.
8.
9.
10.
c. If the logic signals are incorrect, refer to “Analog Bus Timing” and “Analog Bus
Drivers” in this chapter.
Check comparators
A3U109A/C
for proper outputs. The outputs should be high when
the noninverting input is greater than the threshold voltage of
t1.3
Vdc.
If A3U104 and A3U109 are working properly, set the
(AMPLITUDE)
and
REF
LYL to 0
dBm.
Monitor the voltage at
A3TP14
while switching the spectrum analyzer between 10 dB/div
and 2 dB/div. The voltage should switch between 0.8 and 0.4 Vdc.
If the voltage at
A3TP14
is incorrect, suspect either A3Q220 or A3Q221.
The Video MUX will appear faulty if A3CR109 is shorted or leaky. Diode A3CR109
clamps the voltage at
A3TP14
to -0.4 V when in log expand with less than 0.8 V at
JlOl.
To confirm this failure, lift the cathode of diode A3CR109 and perform steps 1
through 7 again.
To return the spectrum analyzer to automatic sweep, press
[s)),
SWFZP
CDNT
SCL or
press
[PRESET).
Video
Filter
Refer to function block V of A3 Interface Assembly Schematic Diagram in the
HP 8560 E-Series Spectrum Analyzer Component Level Information.
The spectrum analyzer uses digital filtering for 1 Hz to 100 Hz video bandwidths. An RC
low-pass filter is used for 300 Hz to 3 MHz video bandwidths. Various series resistances and
shunt capacitances switch into the video filter to change its cutoff frequency.
When sample detection is selected, the effective video bandwidth is limited to approximately
450 kHz by the track and hold circuitry.
When Gated Video is selected, the video signal is “gated” (turned on periodically for a set
duration of time). This function is shown in block V of the block diagram as a series switch
that allows the video signal to pass only when it is closed. The actual switch,
U109B/CR118,
shunts the video to ground (video signal is passed only when the switch is open). The control
circuitry for this switch is described under “Triggering or Video Gating Problems” in this
chapter. The rear-panel EXT/GATE TRIG INPUT provides the connection for triggering in
the Gated Video mode. The gate output signal is available at the rear-panel BLKG/GATE
OUTPUT connector. Positive or negative edge mode, or level mode can be selected from the
front panel.
1. Press
(PRESET)
and set the spectrum analyzer controls to the following settings:
Center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..225MHz
Span . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..550MHz
Sweep time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncoupled (MAN)
2. Press (CAL) and IF
BDJ
[IFF
.
3. Step the Video BW from 3 MHz to 10 kHz. At each step, the peak-to-peak deviation of the
noise should decrease.
4. Step the Video BW down to 1 Hz. At each step, the amplitude of the LO feedthrough
should decrease.
ADC/lnterface
Section 8-17