Agilent Technologies 856290216 Vtrig POL, Lsample, Ladcen, Lloadaddr, Lloadpost, Lvtrig-En

Table 8-13. Control Word at Primary Address (U3 and U4) (continued)

Bit	Mnemonic	State						Description
Bit 2	GAINX2		Turns on X2 log expand amplifier.
		1	A16U43 turned on. (5 dB/div or 1 dB/div scale)
		0	A16U43 turned off. (10 dB/div, 2 dB/div, or linear scale)
Bit 3	VTRIG - POL		Controls digital video trigger polarity.
		1	Negative-edge video trigger.
		0	Positive-edge video trigger.
Bit 4	LSAMPLE		Enables	sample detection mode.
		1	Sample	detection		mode		disabled.
		0	Sample	detection		mode		enabled.
Bit 5	LADCEN		Enables FADC memory for ‘Lwrites”.
			(Toggled in conjunction with bit 0.)
		1	Disables FADC memory for “writes”.
		0	Enables FADC memory for “writes”.
Bit 6	LLOADADDR		Enables load address counter.
		1	“Writes” to the address counter disabled.
		0	“Writes” to the address counter enabled.
Bit 7	LLOADPOST		Enables load post-trigger counter.
		1	“Writes” to the post-trigger counter disabled.
		0	“Writes” to the post-trigger counter enabled.
Bit 8	LVTRIG-EN		Enables digital video trigger on A16.
		1	Digital	video	trigger		disabled.
		0	Digital	video	trigger		enabled.
Bit 9	LREADCLK		Clocks counters during “read” mode. Used to load
			post-trigger counter or address counter. Also used to
			post-increment address counter following memory “reads”.

1

Read clock disabled.

0

Read clock enabled.

ADC/lnterface Section 8-35