Features

Break sequence (transmit data line held “low” for two consecutive stop-bit sequences).

In addition, modem-handshaking line discipline and receive-error detection (such as framing error, data overrun error, and parity error) are built in.

Transmit and receive data are buffered through the on-board Static Random Access Memory (SRAM) and passed between the IPC-1600 and the host processor via the high-speed dual-ported SRAM to enhance system performance.

The IPC-1600 comes with the following standard features:

On-board, high-speed SRAM

Error checking on receive

Input and output data hardware and software flow control.

The serial I/O ports can be mapped into the MS-DOS and UNIX system environments to provide a total of 64 ports (four IPC-1600 boards). When one IRQ level is shared among seven IPC-1600 boards, 112 ports can be supported.

The IPC-1600 base memory address and I/O base address are both configurable via on-board DIP switches.

One IRQ line can be assigned for each IPC-1600 or shared among all equipped IPC-1600s out of a total possible eight interrupts (IRQ3—IRQ5, IRQ7, IRQ10—IRQ12, and IRQ15). A maximum of seven boards can be equipped when one IRQ is shared among all IPC-1600s. A maximum of four board can be equipped when one IRQ is assigned per board.

Eight 8530 serial communications controllers function as dual-channel,

Universal Asynchronous Receiver-Transmitters (DUARTs) to provide a total of sixteen RS-232C channels (ports) complete with the following features:

Programmable baud rates, data bits, parity bits, stop bits

Control of DTR, RTS, and TD

Detection of RD, CTS, DCD, RI, and BREAK.

6-2 IPC-1600 USER’S GUIDE

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AT&T IPC-1600 manual Features