Table | 1-1 PCI/PCI-X I/O Rope Groups (continued) | |
Slot # | | Rope Numbers | PCI Bus | Bits | Speed | Function | Hot Swap / |
| | | | | | | OL* |
| | | | | | | |
6 | | 2, 3 (Dual | 5 | 64 | 133 MHz | High-Speed PCI-X (Public) | Y |
| | Bandwidth) | | | | | |
| | | | | | | |
7, 8 | | 9 | 6 | 64 | 66 MHz | General PCI-X (Public) | Y |
| | | | | | | |
9, 10 | | 1 | 7 | 64 | 66 MHz | General PCI-X (Public) | Y |
| | | | | | | |
- | 0 | 0 | 32 | 33 MHz | UCIO (Private) | N |
| | | | | | | |
PCI/PCI-X/PCIe IOBP
On the 10 slot PCI/PCI-X/PCIe IOBP there are a total of eight Public slots (four PCI-X mode 1 and four PCIe), two Private Fast-core slots (PCI/PCI-X mode 1 64-bit/66-MHz), and one Private Slow-core UCIO slot (PCI 32-bit/33-MHz). The eight Public slots are further divided into three speed/bandwidth configurations:
•Two PDHP, which operate at 64-bit/66-MHz PCI-X
•Two PSHP, operating at 64-bit/133-MHz PCI-X
•Four PCIe 8-lane (x8) 2.5 Gbps, two of which are switched
The two 66 MHz PCI/PCI-X slots are shared. Shared slots have many speed and mode change restrictions during hot-plug add or remove operations.
Table | 1-2 PCI/PCI-X/PCIe I/O Rope Groups | | |
| | | | | | |
Slot # | | Rope Numbers | Bits | Speed | Function | Hot Swap/OLR |
| | | | | | |
1, 2 | | 8 | 64 | 66 MHz | Core I/O (Private) | N |
| | | | | | |
3, 4 | | 10, 11 | x8 | 2.5 Gbps | PCIe x8 (Public or Private depending upon | N |
| | | | | Core I/O) | |
| | | | | | |
5 | | 12, 13, 14, 15 | x8 | 2.5 Gbps | PCIe x8 (Public) | Y |
| | | | | | |
6 | | 4, 5, 6, 7 | x8 | 2.5 Gbps | PCIe x8 (Public) | Y |
| | | | | | |
7 | | 2, 3 | 64 | 133 MHz | High-Speed PCI-X (Public) | Y |
| | | | | | |
8 | | 9 | 64 | 133 MHz | High-Speed PCI-X (Public) | Y |
| | | | | | |
9, 10 | | 1 | 64 | 66 MHz | General PCI-X (Public) | Y |
| | | | | | |
- | 0 | 32 | 33 MHz | UCIO (Private) | N |
| | | | | | |
PCIe MPS Optimization
For PCIe-based systems, each PCIe device has a configurable MPS (maximum payload size) parameter. Larger MPS values can enable the optimization to gain higher performance.MPS Optimization is supported on PCIe systems running HP-UX, Open VMS, and Linux. System firmware level greater than 02.03 performs an optimization during boot time to set the MPS value to the largest size supported by both a PCIe root port and the devices below it.
The default server state is optimization disabled. When disabled system firmware sets MPS to the minimum value on each PCIe device.
The info io command will display the current PCIe MPS optimization setting. See “info” (page 328).
To enable PCIe MPS optimization use the ioconfig mps_optimize command. See “ioconfig” (page 326).
For non-PCIe systems, ioconfig and info io will not display the MPS optimization policy setting. The Set PCIe MPS Optimization boot manager menu also will not be displayed. Running