the ioconfig mps_optimize [onoff] command from a non-PCIe system, the following output will be displayed:

-------------

Shell> ioconfig mps_optimize

ioconfig: PCIe MPS optimization is not supported.

Shell> ioconfig mps_optimize on

ioconfig: PCIe MPS optimization is not supported.

Exit status code: Unsupported

Shell>

-----------------

To restore MPS to the default values use the default clear command. See “default” (page 327).

Processor

The server processor subsystem accommodates one or two dual-core Itanium® processor modules. The processor subsystem consists of the following elements:

zx2 CEC front side bus, memory, and I/O controller

System clock generation and distribution

Circuitry for manageability and fault detection

The zx2 CEC and the processor modules are located on the processor board assembly. Each processor connects to the processor board through a zero insertion force (ZIF) socket. The processor board is mounted on a removable carrier tray that is attached to the processor board access door. Access the assembly through the front of the server after the memory carrier is removed.

Memory

The server DIMMS are seated on memory boards that are enclosed in an extractable memory carrier assembly. The memory boards plug directly into sockets on the processor board when the memory carrier assembly is fully seated.

Table 1-3lists the two types of supported memory carriers and the memory configurations of each carrier.

Table 1-3 Supported Memory Configurations

Memory Carrier Type

Memory Boards Installed

Minimum Memory

Maximum Memory

 

 

Configuration

Configuration

 

 

 

 

8-DIMM memory carrier

Two 4-DIMM memory

2-GB (one pair: two 1-GB

32-GB (eight 4-GB DIMMs)

(standard)

boards

DIMMs)

 

 

 

 

 

24-DIMM memory carrier

Two 12-DIMM memory

2-GB (one quad: four

96-GB (24x4-GB DIMMs)

(optional, high-capacity)

boards

512-MB DIMMs)

 

 

 

 

 

The server supports the following DIMM sizes:

512-MB

1-GB

2-GB

4-GB

Figure 1-3is a block diagram of the 8-DIMM memory carrier that shows data, addresses, and controls that flow through the CEC and to and from the processors.

Server Subsystems

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