Figure
System POL Converters
Fan contlr
12/5/06POL
Processor BP
| CPU PODS |
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| Fan contlr |
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| V12 | POL |
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V12 | (2) |
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| V1P 2 |
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V12 | POLSummit |
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| LoopSummit |
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| Mem Ext | (2) |
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| V1P 5 |
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V12 | POL | 12/24 DIMM |
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| Summit | V1P 2 |
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| Loop |
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| V12 | POL |
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| Summit |
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| V1P 8 |
| Loop |
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V12 | POL |
| V1P 8 |
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| Summit |
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| Loop |
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| V12 | POL |
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| Summit |
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| Loop |
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| V2P 5 |
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V12 | POL | V3P 3_STBY | V0P 9 |
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| Summit |
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| embedded |
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| Loop |
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| V2P5 |
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| 12/24 DIMM |
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| B Y |
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| V12 | 3 S T | |
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| V3P 3_STBY |
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| V3P |
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Possibly share Source and Load |
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| BPS |
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Processor Side | (2) |
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| I/O BP |
| PDH |
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| V1P 2 |
| V2P 5 |
| Unified Core |
V12 | POL |
| POL |
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| Summit |
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| V3P3 is called |
| Loop |
| V12 |
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| V1P 5 |
| Summit | V3P3_PCI | |
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| Loop | ||
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V12 | POL Summit |
| V1P 0 |
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| Loop |
| POL |
| V1P 2_FPGA |
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| V12 |
| embedded | |
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| V5P 0 |
| Tower of Power |
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V12 | POL |
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| V5P0 | V2P 5_FPGA |
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| V3P 3 |
| embedded |
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| V3P3 |
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V3P 3_STBY |
| V12 | POL |
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| V1P 8_SYS _PLL | |||
| V12N |
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| embedded | |
V12 | POL |
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| V1P 8_RMP 3 |
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| V3P 3_STBY | embedded | ||
Interconnect |
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| Embedded design | ||
V3P 3_STBY |
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| CCA |
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| FPD CCA | ||
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| V3P3 |
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V12 | V3P3 |
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| V3P3 |
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| V3P 3_STBY | V5P 0 |
| V3P 3_STBY | |
| Socha, Jim | SAS CCA | |||
CIOBP | – Target CCA |
| POL | ||
V12 |
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| V3P3 |
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V5P0
I/O Side | V12 |
Two
Applying system power in normal customer usage, the rx3600 runs on 100 to 240 V. Standby power will be supplied on either; hence the BMC will power up when the power supplies are plugged in. The BPS0_AC_OK and BPS1_AC_OK signals indicate whether the ac voltage to the power supplies is within the required range. If neither BPS0_AC_OK nor BPS1_AC_OK is asserted, then the BMC should log an event and prevent the system from turning on.
Power Button The power button on the rx3600 is a momentary contact push button. The BMC polls the front panel power button at a rate of at least 2 Hz. The power button is an input to the System Power State Management. If the system is off, a single button press will turn on the system. If the system has booted to an OS, and a short button press is detected, a
System Power State Management The system power may be controlled from the power button, an IPMI Chassis command,
Power On Sequence:
1.Update the cache of DIMM SPD information.
2.Ensure that the memory board is detected and that the cpu board has a processor in socket 0. If these FRUs are not detected the BMC logs an event against the Missing Device sensor (sensor 0x15).
3.Check for a BPS0_AC_OK or a BPS1_AC_OK signal. If neither is asserted, then the ac supply has a problem.
4.If any FRUs are missing or both ac supplies are not valid, then return to power off state.
Server Subsystems 33