Intel MPCMM0001 Bist Flow Chart, Bist Implementation, Boot-BIST Early-BIST Mid-BIST Late-BIST

Built-In Self Test (BIST)

Figure 1.	BIST Flow Chart
				Jump to
				run from
				RB
			RB image pass
		Run from	RB image	RB image fail	FPGA image
Power Up/			and backup		and backup
	Reset	backup	RB image		FPGA image
		RB	checksum		checksum
				backup FPGA	NOT (backup
				image pass	FPGA image
	BlueCat			and FPGA	pass and
				image fail	FPGA image
	loaded (active
					fail)
	CMM)
				Load backup	Load FPGA
				FPGA image	image
	IPMB
	Bus Test
	BlueCat	FPGA,		Memory Test
	Image	DS1307, NIC
	Checksum

The BIST has been broken down into stages consisting of groups of tests that run at certain times throughout the boot process. The following table shows the different BIST stages and the tests associated with each stage:

Table 4. BIST Implementation

Boot-BIST	Early-BIST	Mid-BIST	Late-BIST
RedBoot image	Strobe WDT to extend	Extended memory test	BlueCat image checksum
checksum	timeout period
FPGA image checksum		FPGA version check	IPMB bus test
Base memory test		DS1307 RTC test
		Local PCI bus/NIC
		presence test

32MPCMM0001 Chassis Management Module Software Technical Product Specification