Compaq EV68A manuals
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Compaq EV68A Specifications
356 pages 4.11 Mb
2 21264/EV68A Hardware Reference Manual3 Table of Contents17 Preface25 Introduction29 Internal Architecture69 Hardware Interface89 Cache and External Interfaces143 Internal Processor Registers144 MboxIPRsTable 51 Internal Processor Registers (Con tinued) 145 5.1 Ebox IPRs148 5.2 Ibox IPRs167 5.3 Mbox IPRs174 5.4 CboxCSRsandIPRs175 5.4.1 Cbox Data Register C_DATAFigure 535shows the Cbox data register. Table522 describes the Cbox data register fields. 5.4.2 Cbox Shift Register C_SHFTFigure 536shows the Cbox shift register. Table523 describes the Cbox shift register fields. 5.4.3 Cbox WRITE_ONCE Chain DescriptionThe WRITE_ONCE chain order is containedin Table 524. In the table: 176 CSRs is containedin C hapter4. chain. Table524 describes the Cbox WRITE_ONCE chain order from LSB to MSB. 180 5.4.4 Cbox WRITE_MANY ChainDescriptionThe WRITE_MANY chainorder is contained in Table 525. Note the following: CSRs is containedin C hapter3. are indicatedin italics and have two leading asterisks. 181 chain. Table525 describes the Cbox WRITE_MANY chain order from LSB to MSB. Figure 537shows an example of PALcode used to write to the WRITE_MANY chain. 185 Privileged Architecture Library Code209 Initialization and Configuration229 Error Detection and Error Handling241 Electrical Data251 Thermal Management257 Testability and Diagnostics265 A283 B21264/EV68A Boundary-Scan RegisterThis appendixcontains the BSDL description of the 21264/EV68A boundary-scan reg- ister. B.1 Boundary-ScanRegisterB.1.1 BSDL Description of the Alpha 21264/EV68A Boundary-Scan Register 297 DPALcode Restrictions and GuidelinesD.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper 304 D.2 Restriction 2 : No Multi ple Writers to IPRs in Same Scoreboard GroupD.3 Restriction 4 :NoWritersandReaderstoIPRsinSameScore- board GroupGuideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write 305 D.4 Guideline 6 :Avoid Consec utive Read-Modify-Write-Read- Modify-WriteD.5 Restriction 7 : Replay Trap, Interrupt Code Sequence,and STF/ ITOFRestriction 9 : PALmodeIstream Address Ranges 306 D.6 Restriction 9 : PALmode Istream AddressRangesD.7 Restriction 10: Duplicate IPR Mode BitsRestriction 11: IboxIPR Update Synchronization 307 D.8 Restriction 11: Ibox IPR UpdateSynchronizationD.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM D.10 Restriction 13 : DTB Fill Flow Collision D.11 Restriction 14 : HW_RETRestriction 22: HW_RET/STALLAfter HW_MTPR IS0/IS1 309 D.18 Restriction22: HW_RET/STALL After HW_MTPR IS0/IS1D.19 Restriction 23: HW_ST/P/CONDITIO NAL DoesN ot Clear the Lock FlagRestriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, 310 D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAPD.21 Restriction25: HW_MTPR ITB_IA After Reset D.22 Guideline 26: C onditional Branches in PALcodeRestriction 27: Reset of Force-FailLock Flag State in PALcode 311 D.23 Restriction2 7: Reset of Force-Fail Lock Flag State in PALcodeD.25 Guid eline 29 : JSR, JMP,RET, and JSR_COR in PALcode D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR 313 D.27 Restriction 31 : I_CTL[VA_48] UpdateD.28 Restriction 32 : PCTR_CTL UpdateRestriction 33 : HW_LD Physical/LockU se 314 D.29 Restriction 33 : HW_LD Physical/Lock U seD.30 Restriction34 : Writing Multiple ITB Entries in theSame PAL- code Flow D.31 Guideline 35 : HW_INT_CLR Update D.32 Restriction 36 : Updating I_CTL[SDE] D.33 Restriction 37 : Updating VA_CTL[VA_48] D.34 Restriction 38 : Updating PCTR_CTLGuideline 39: Writing MultipleDTB Entries in the Same PAL Flow 315 D.35 Guideline 39: Writing Multiple DTB Entries in the Same PAL FlowD.36 Restriction 40: Scrubbing a Single-Bit Error 318 D.42 Restriction 46: Avoiding Livelocks in SpeculativeLoad CRD HandlersD.43 Restriction 47: Cache Eviction for Single-Bit Cache Er rors 321 E
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