Main
21264/EV68A Hardware Reference Manual
Table of Contents
Preface 1 Introduction
2 Internal Architecture
21264/EV68A Hardware Reference Manual
3 Hardware Interface
4 Cache and ExternalInterfaces
5 Internal Processor Registers
21264/EV68A Hardware Reference Manual
6 PrivilegedArchitecture Library Code
7 Initialization and Configuration
21264/EV68A Hardware Reference Manual
8 Error Detectionand Error Handling
9 Electrical Data
10 ThermalManagement
11 Testabilityand Diagnostics
A Alpha Instruction Set
B 21264/EV68A Boundary-ScanRegister
C Serial Icache Load PredecodeValues D PALcode Restrictionsand Guidelines
E 21264/EV68A-to-Bcache Pin Interface
Glossary Index
Figures
21264/EV68A Hardware Reference Manual
Tables
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Preface
Audience
Content
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Terminologyand Conventions
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A capital X represents any valid value.
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Introduction
1.1 The Arc hitecture
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1.2 21264/EV68A Microprocessor Fe atures
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Internal Architecture
2.1 21264/EV68A Microarchitecture
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InternalArchitecture
Figure 21 2126 4/EV68A Block Diagram
2.1.1.2 Branch P redictor
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2.1.2 Integer Execution Unit
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2.1.7 SROM Interface
2.2 Pipeline Orga nization
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2.2.1 Pipeline Aborts
2.3 Instructio n Issue Rules
2.3.1 Instruction Group Definitions
2.3.2 Ebox Slotting
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2.3.3 Instruction Latencies
Instruction Retire Rules
2.4 Instruction RetireRules
2.5 Retire of Op erate Instructions into R31/F31
Load Instructionsto R31 and F31
2.6 Load Instructions to R31 and F3 1
2.6.1 NormalPre fetch:L DBU, LDF,LDG, LDL, LDT,LDWU, HW_LDL In structions
2.6.2 Prefetch with Modify Intent: LDS Instruction
2.7 Speci al Cases of Alpha Instruction Execution
2.7.1 Load Hit Speculation
Special Cases of AlphaInstruction Execution
Special Cases of Alpha Instruct ion Execution
2.7.2 Floating-Point StoreInstructions
2.7.3 CMOV Instruction
Memory andI/O Address Space Instructions
2.8 Memory and I/O Address Space Instruction s
2.8.1 MemoryAddress Space Load Instructions
2.8.2 I/OAddress Space Load Instructions
Memory and I/O Address Space Instructions
2.8.3 MemoryAddress Space Store Instructions
Memory andI/O Address Space Instructions
2.8.4 I/O Address Space Store Instructions
MAF Memory Address SpaceMerging Rules
2.9 MAF Memory Address Space Merging Rules
2.10 InstructionOrdering
Replay Traps
2.11 R eplay Traps
2.11.1 Mbox Order Traps
2.12 I/O Writ e Buffer and the WMB Instruction
I/O Write Buffer and the WMB Instruction
I/O Write Buffer andthe WMB Instruction
Performance MeasurementSupportPerformance Counters
2.13 Performance Measurement SupportPerformanceCounters
2.14 Floating-Point Control Register
21264/EV68A Hardware Reference Manual
Floating-PointControl Register
The floating-pointcontrol register fields are described in Table 214.
AMASK and IMPLVER Instruction Values
2.15 AMASK and IMPLVERInstruction Values
Design Examples 2.15.1 AMASK
2.15.2 IMPLVER
2.16 Design Examples
InternalArchitecture
Design Examples
Figure 213 Typical Multiprocessor Configuration
Figure 212 Typical Uniprocessor Configuration
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Hardware Interface
3.1 21264/EV68A Microproces sor Logic Symbol
32 Hardware Interface
21264/EV68A MicroprocessorLogic Symbol
Figure 31 21264/EV68A Microprocessor Logic Symbol
3.2 21264/EV68ASignal Names and Functions
Table31 defines the 21264/EV68A signal types referred to in this section.
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Table33 lists signals by function and provides an abbreviated description.
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3.3 Pin Assignments
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Hardware Interface
Table 35 Pin Li stSo rted by PGA Location
Table 34 PinList Sorted by Signal Name (Continued)
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Hardware Interface
Table36 lists the 21264/EV68A ground and power (VSS and VDD, respectively) pin list.
Table 36 Ground and Power (VSS and VDD) Pin Lis t
Hardware Interface
Mechanical Specifications
3.4 Mechanical Specifications
Figure 32 Package Dimensions
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Cache and External Interfaces
4.1 Introduct ion to the External Interfaces
Introductionto the External Interfaces
Cache and External Interfaces
Introduction to the Externa l Interfaces
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Figure 41 2126 4/EV68A System and Bcache Interfaces
4.1.1 System Interface
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4.2 Physical Address Considerat ions
Physical AddressConsiderations
Physical Address Considerations
Bcache Structure
4.3 Bcache Structure
4.3.1 Bcache Interface Signals
4.3.2 SystemDuplicate Tag Stores
4.4 Victim Data Buffer
4.5 Cac he Coherency
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4.5.3 Cache Block State Transitions
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4.5.5 DcacheStates and Duplicate Tags
Lock Mechanism
4.6 Loc k Mechanism
Lock Mechanism 4.6.1 In-Order Processingof LDx_L/STx_C Instructions
4.6.2 Internal Eviction of LDx_L Blocks
4.6.3 Liveness and Fairness
4.6.4 Managing Speculative Store Issues with MultiprocessorSystems
4.7 Syste m Port
4.7.1 System Port Pins
4.7.2 Programming the SystemInterface Clocks
4.7.3 21264/EV68A-to-SystemCommands
Table411 shows the command format for page hit mode (21264/EV68A-to-system).
Table412 describes the field definitions for Tables 410 and 411.
4.7.4 21264/EV68A-to-SystemCommands Descriptions
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4.7.5 ProbeResponse Commands(Command[4:0] = 00001)
4.7.6 SysAck and 21264/EV68A-to-SystemCommands Flow Control
4.7.7 System-to-21264/EV68A Commands
Table420 describes the system-to-21264/EV68A probe commands fields descriptions.
Table422 lists the next cache block state selected by Probe[2:0].
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4.7.8 Data Movement In and Out of the 21264/EV68A
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4.7.9 Nonexistent Memory Processing
Table432 shows each 21264/EV68A command, with NXM addresses, and the appro- priatesystem response.
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21264/EV68Afails the STx_C instruction as defined in the AlphaArchitecture Handbook,Version 4
becausethe 21264/EV68A does not yet own the block.
4.8 Bcache Port
4.8.1 Bcache Port Pins
4.8.2 Bcache Clocking
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4.8.3 Bcache Transactions
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4.8.4 Pin Descriptions
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4.8.5 Bcache Banking
4.8.6 Disabling the Bcache for Debugging
Interrupts
4.9 Interrupts
Internal Processor Registers
MboxIPRs
Table 51 Internal Processor Registers (Con tinued)
5.1 Ebox IPRs
5.1.1 Cycle Counter Register CC
5.1.2 Cycle Counter Control Register CC_CTL
5.1.3 Virtual AddressRegister VA
5.1.4 Virtual AddressControl Register VA_CTL
5.1.5 Virtual AddressFormat Register VA_FORM
5.2 Ibox IPRs
5.2.1 ITB Tag Array Write Register ITB_TAG
5.2.2 ITB PTE Array Write Register ITB_PTE
5.2.3 ITB Invalidate All Process (ASM=0) Register ITB_IAP
5.2.4 ITB Invalidate All Register ITB_IA
5.2.5 ITB Invalidate Single Register ITB_IS
5.2.6 ProfileMe PC Register PMPC
5.2.7 Exception Address Register EXC_ADDR
5.2.8 Instruction VirtualAddress Format Register IVA_FORM
5.2.9 Interrupt Enable and CurrentProcessor Mode Register IER_CM
Table55 describes the interrupt enable and current processormode register fields.
5.2.10 Software Interrupt Request Register SIRR
5.2.11 Interrupt Summary Register ISUM
Table57 describes the interrupt summary register fields.
5.2.12 Hardware InterruptClear Register HW_INT_CLR
5.2.13 Exception Summary Register EXC_SUM
Table59 describes the exception summary register fields.
5.2.14 PAL Base Register PAL_BASE
5.2.15 Ibox Control Register I_CTL
Table511 describes the Ibox control register fields.
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5.2.16 Ibox StatusRegister I_STAT
Table512 describes the Ibox status register fields.
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5.2.17 Icache Flush Register IC_FLUSH
5.2.18 Icache Flush ASM Register IC_FLUSH_ASM
5.2.19 Clear Virtual-to-PhysicalMap Register CLR_MAP
5.2.20 Sleep Mode Register SLEEP
5.2.21 Process Context Register PCTX
Table514 describes the process context register fields.
5.2.22 Performance Counter Control Register PCTR_CTL
Table515 describes the performance counter control registerfields.
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5.3 Mbox IPRs
5.3.1 DTB Tag Array Write Registers 0 and1 DTB_TAG0, DTB_TAG1
5.3.2 DTB PTE Array Write Registers 0 and 1 DTB_PTE0, DTB_PTE1
5.3.3 DTB Alternate Processor Mode Register DTB_ALTMODE
5.3.4 Dstream TB Invalidate A ll Process (ASM=0) Register DTB_IAP
5.3.5 Dstream TB Invalidate All Register DTB_IA
5.3.6 Dstream TB Invalidate Single Registers 0 and 1 DTB_IS0,1
5.3.7 Dstream TB Address Space Number Registers 0 and 1 DTB_ASN0,1
5.3.8 Memory Management Status Register MM_STAT
the Ibox EXC_SUM register.
5.3.9 Mbox Control Register M_CTL
Table519 describes the Mbox control register fields.
erencesto superpagesresult in access violations.
5.3.10 Dcache Control Register DC_CTL
Table520 describes the Dcache control register fields.
5.3.11 Dcache Status Register DC_STAT
5.4 CboxCSRsandIPRs
5.4.1 Cbox Data Register C_DATA
Figure 535shows the Cbox data register.
Table522 describes the Cbox data register fields.
5.4.2 Cbox Shift Register C_SHFT
Figure 536shows the Cbox shift register.
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5.4.4 Cbox WRITE_MANY ChainDescription
The WRITE_MANY chainorder is contained in Table 525. Note the following:
CSRs is containedin C hapter3.
are indicatedin italics and have two leading asterisks.
chain. Table525 describes the Cbox WRITE_MANY chain order from LSB to MSB.
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Privileged Architecture Library Code
6.1 PALcode Description
PALmode Environment
6.2 PALmodeEnvironment
Required PALcodeFunction Codes
6.3 Required PALcodeFunction Codes
6.4 Opcodes Reserved for PALcode
6.4.1 HW_LD Instruction
Opcodes Reserved for PALcode
Table63 describes the HW_LD instruction fields.
6.4.2 HW_ST Instruction
Opcodes Reserved forP ALcode
6.4.3 HW_RET Instruction
Opcodes Reserved for PALcode
Table65 describes the HW_RET instruction fields.
6.4.4 HW_MFPR and HW_MTPR Instructions
Internal ProcessorRegister Access Mechanisms
6.5 Internal Processor Register Access Mechanisms
Internal ProcessorR egisterAccess Mechanisms 6.5.1 IPR Scoreboard Bits
6.5.2 Hardware Structure of Explicitly Written IPRs
Internal ProcessorRegister Access Mechanisms 6.5.3 Hardware Structure of Implicitly Written IPRs
6.5.4 IPR Access Ordering
Internal ProcessorR egisterAccess Mechanisms
6.5.5 Correct Ordering of Explicit Writers Followed by Implicit Readers
PALshadow Registers 6.5.6 Correct Ordering of Explicit Readers Followed by Implicit Writers
6.6 PALshadow Registers
6.7 PALcode Emulationof the FPCR
PALcode Entry Points
6.7.1 StatusFlags
6.7.2 MF_FPCR
6.8 PALcode EntryPoints
6.8.1 CALL_PALEntry Points
PALcode Entry Points
6.8.2 PALcode Exception Entry Points
Translation Buffer(TB) Fill Flows
6.9 TranslationBuffer (TB) Fill Flows
6.9.1 DTBFill
Figure 65 shows single-missDTB instructions flow.
Translation Buffer (TB) Fill Flows
Translation Buffer(TB) Fill Flows
6.9.2 ITB Fill
6.10 Performance CounterSupport
6.10.1 General Precautions
6.10.2 Aggregate Mode Programming Guid elines
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6.10.3 ProfileMe Mo de Programming Guidelines
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Table614 shows the counter modes that are used with ProfileMe mode.
Initialization and Configuration
7.1 Power-Up Reset Flowand the Reset_L and DCOK_H Pins
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7.1.1 Power Sequencing and Reset State for SignalPins
7.1.2 Clock Forwarding and System Clock Ratio Configuration
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7.1.3 PLL Ramp Up
7.1.4 BiST and SROM Load and the TestStat_HPin
7.1.5 Clock Forward Reset and System Interface Initialization
Fault Reset Flow
7.2 Fault Reset Flow
Energy Star Certificationand Sleep Mode Flow
7.3 Energy Star Certi fication and Sleep Mode Flow
Energy Star Certificationand Sleep Mode Flow
Warm Reset Flow
Table77 describes each signal and constraint for the sleep modesequence.
7.4 Warm Reset Flow
Array Initialization
7.5 Array Initialization
7.6 Initialization Mode Pr ocessing
Initialization Mode Processing
External InterfaceInitialization
7.7 ExternalInte rface Initialization
7.8 Internal Processor Register Power-UpReset State
Internal ProcessorRegister Power-Up Reset State
IEEE 1149.1 Test PortReset
7.9 IEEE 1149.1 Test Port Reset
7.10 Reset State Machine
Initialization and Configuration
Reset State Machine
Figure 75 2126 4/EV68A Reset State Machine State Diagram
Table 711 21264/E V68AR eset State Machine State Descriptions
StateName Description
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Phase-Lock Loop (PLL) FunctionalDescription
7.11 Phase-Lock Loop (PLL) Functional Description
7.11.1 DifferentialReference Clocks
7.11.2 PLLOutput Clocks
Phase-Lock Loop(PLL) Functional Description
Error Detection and Error Handling
Data Error Correction Code
8.1 Data Error Correction Code
8.2 Icache Data or Tag Parity Error
8.3 Dcache Tag Parity Error
8.4 DcacheData Single- Bit Correctable ECC Error
8.5 Dcach e Store Second Error
8.6 Dcach e Duplicate TagPar ity Error
8.7 Bcache Tag Parity Error
8.8 Controlling Bcache Block Parity Calculat ion
8.9 Bcache Data Single-Bit Correctable ECC Error
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8.10 Memory/System Port Single-Bit DataCorrectable ECC Error
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8.11 Bcache Data Single-Bit Correctable ECC Error on a Probe
8.12 Double-BitFill Errors
Error Case Summary
8.13 Error Case Summary
Table83 summarizes the various error cases and their ramifications.
Error CaseSummary
D.36
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Electrical Data
9.1 Electr ical Characteristics
9.2 DC Characteristics
symbolindicates current flowing into a 21264/EV68A pin.
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Power Supply Sequencing andAvoiding Potential Failure Mechanisms
9.3 Power Supply Sequencingand Avoiding PotentialFailure Mech- anisms
9.4 AC Characteristics
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98 ElectricalDat a
Table 913 AC Specifications (Continued)
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Thermal Management
10.1 Operating Temperature
Operating Temperature
10.2 Heat Sink Specifications
104 Thermal Management
Figure 102shows the heat sink type 2, along with its approximate dimensions.
Figure 102 T ype2 H eatSi nk
Thermal Management
Figure 103 Ty pe3 H eatSi nk
10.3 Thermal Design Considerations
Testability and Diagnostics
11.1 Test P ins
11.2 SROM/Serial Diagnostic TerminalPort
IEEE 1149.1 Port
11.3 IEEE 114 9.1 Port
114 Testability and Diagnostics
TestStat_H Pin
Scan SequenceScan Sequence
Table 113 TAP Controller State Machine
11.4 TestStat_H Pin
Note: A system designerm ay sample the TestStat_Hpin on the first rising edge
Power-Up Self-Test and Initialization
11.5 Power-Up Self-Test and Initialization
11.5.1 Built-in Self-Test
11.5.2 SROM Initialization
Power-Up Self-Test and Initialization
Notes on IEEE 1149.1Operation and Compliance
11.6 Noteson IEEE 1149.1 Operationand Compliance
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A
Alpha Instruction Set
A.1 Alpha Instru ction Summary
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Reserved Opcodes
A.2 Reserved Opcodes
A.2.1 Opcodes Reserved for Compaq
IEEE Floating-PointInstructions A.2.2 Opcodes Reserved for PALcode
A.3 IEEE Floating-Point Inst ructions
IEEE Floating-Point Instr uctions
VAX Floating-Point Instructions
A.4 VAX Floating-Point Instructions
A.5 Independent Floating-Point Instructions
Opcode Summary
A.6 Opcode Summary
Required PALcodeFunction Codes
A.7 Required PALcodeFunction Codes
A.8 IEEE Floating-Point Co nformance
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See Section2.14 for information about the floating-point control register (FPCR).
21264/EV68A Boundary-Scan Register
B
21264/EV68A Boundary-Scan Register
This appendixcontains the BSDL description of the 21264/EV68A boundary-scan reg- ister.
B.1 Boundary-ScanRegister
B.1.1 BSDL Description of the Alpha 21264/EV68A Boundary-Scan Register
B2 21264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register
B4 21264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register
B6 21264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register
B8 21264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register
B10 21264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register
B12 21264/EV68A Boundary-Scan Register
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PALcode Restrictions and Guidelines
D
PALcode Restrictions and Guidelines
D.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
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PALcode Restrictions and Guidelines
Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group
D.2 Restriction 2 : No Multi ple Writers to IPRs in Same Scoreboard Group
D.3 Restriction 4 :NoWritersandReaderstoIPRsinSameScore- board Group
Guideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write
D.4 Guideline 6 :Avoid Consec utive Read-Modify-Write-Read- Modify-Write
D.5 Restriction 7 : Replay Trap, Interrupt Code Sequence,and STF/ ITOF
Restriction 9 : PALmodeIstream Address Ranges
D.6 Restriction 9 : PALmode Istream AddressRanges
D.7 Restriction 10: Duplicate IPR Mode Bits
Restriction 11: IboxIPR Update Synchronization
D.8 Restriction 11: Ibox IPR UpdateSynchronization
D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM
D.10 Restriction 13 : DTB Fill Flow Collision
D.11 Restriction 14 : HW_RET
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Restriction 22: HW_RET/STALLAfter HW_MTPR IS0/IS1
D.18 Restriction22: HW_RET/STALL After HW_MTPR IS0/IS1
D.19 Restriction 23: HW_ST/P/CONDITIO NAL DoesN ot Clear the Lock Flag
Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM,
D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP
D.21 Restriction25: HW_MTPR ITB_IA After Reset
D.22 Guideline 26: C onditional Branches in PALcode
Restriction 27: Reset of Force-FailLock Flag State in PALcode
D.23 Restriction2 7: Reset of Force-Fail Lock Flag State in PALcode
D.25 Guid eline 29 : JSR, JMP,RET, and JSR_COR in PALcode
D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR
Restriction30 : HW_MTPR and HW_MFPRto the Cbox CSR
Restriction 31 : I_CTL[VA_48]Update
D.27 Restriction 31 : I_CTL[VA_48] Update
D.28 Restriction 32 : PCTR_CTL Update
Restriction 33 : HW_LD Physical/LockU se
D.29 Restriction 33 : HW_LD Physical/Lock U se
D.30 Restriction34 : Writing Multiple ITB Entries in theSame PAL- code Flow
D.31 Guideline 35 : HW_INT_CLR Update
D.32 Restriction 36 : Updating I_CTL[SDE]
D.33 Restriction 37 : Updating VA_CTL[VA_48]
D.35 Guideline 39: Writing Multiple DTB Entries in the Same PAL Flow
D.36 Restriction 40: Scrubbing a Single-Bit Error
Restriction 40: Scrubbinga Single-Bit Error
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Restriction 46: AvoidingLivelocks in Speculative Load CRD Handlers
D.42 Restriction 46: Avoiding Livelocks in SpeculativeLoad CRD Handlers
D.43 Restriction 47: Cache Eviction for Single-Bit Cache Er rors
PALcode Restrictions and Guidelines
Restriction 47: Cache Evictionfor Single-Bit Cache Errors
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E
21264/EV68A-to-Bcache Pin Interface
This appendixprovides the pin interface b etween the21264/EV68A and Bcache SSRAMs.
E.1 Forwarding ClockPin Groupings
Late-Write Non-Bursting SSRAMs
E.2 Late-Write Non-Bursting SSRAM s
Unused Bcachetag pins should be pulled to ground through a200-ohm resistor.
Data Pin Usage
Tag Pin Usage
Dual-Data Rate SSRAMs
E.3 Dual-Data Rate SSRAMs
Data Pin Usage
Dual-Data RateSSRAMs
Tag Pin Usage
Unused Bcachetag pins should be pulled to ground through a200-ohm resister.
Dual-Data Rate SSRAMs
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Glossary
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Index
Numerics
A
B
C
D
E
F
G
H
I
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J
L
M
N
O
P
R
S
T
U
V
W
X