Compaq EV68A Instruction Retire Rules, Minimum Retire Latencies for Instruction Classes

Instruction Retire Rules

Table 2–4 Instruction Class Latency in Cycles (Continued)

Class	Latency	Comments
fadd	4	Consumer other than fst or ftoi.
	6	Consumer fst or ftoi.
		Measured from when an fadd is issued from the FQ to when an fst or ftoi is issued
		from the IQ.
fmul	4	Consumer other than fst or ftoi.
	6	Consumer fst or ftoi.
		Measured from when an fmul is issued from the FQ to when an fst or ftoi is issued
		from the IQ.
fcmov1	4	Only consumer is fcmov2.
fcmov2	4	Consumer other than fst.
	6	Consumer fst or ftoi.
		Measured from when an fcmov2 is issued from the FQ to when an fst or ftoi is
		issued from the IQ.
fdiv	12	Single precision - latency to consumer of result value.
	9	Single precision - latency to using divider again.
	15	Double precision - latency to consumer of result value.
	12	Double precision - latency to using divider again.
fsqrt	18	Single precision - latency to consumer of result value.
	15	Single precision - latency to using unit again.
	33	Double precision - latency to consumer of result value.
	30	Double precision - latency to using unit again.
ftoi	3	—
itof	4	—
nop	—	Does not produce register value.

2.4 Instruction Retire Rules

An instruction is retired when it has been executed to completion, and all previous instructions have been retired. The execution pipeline stage in which an instruction becomes eligible to be retired depends upon the instruction’s class.

Table 2–5gives the minimum retire latencies (assuming that all previous instructions have been retired) for various classes of instructions.

Table 2–5 Minimum Retire Latencies for Instruction Classes

Instruction Class	Retire Stage	Comments
Integer conditional branch	7	—
Integer multiply	7/13	Latency is 13 cycles for the MUL/V instruction.
Integer operate	7	—
Memory	10	—
Floating-point add	11	—
Floating-point multiply	11	—

21264/EV68A Hardware Reference Manual Internal Architecture 2–21